Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1998-06-24
2000-11-28
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
714 42, G11C 2900
Patent
active
061548626
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a failure analysis memory for semiconductor memory testing apparatus and, more particularly, to a failure analysis memory for memory testing apparatus which speeds up what is called a remove operation and hence reduces the time for testing semiconductor memories
2. Description of the Prior Art
Referring first to FIG. 1, a prior art example of memory testing apparatus will be described in brief.
In the testing of semiconductor memories, a pattern generator 20 responds to a reference clock CLK from a timing generator 10 to generate an address AD, test data TD, expectation data ED and a control signal CS. The address AD, the test data TD and the control signal CS are each shaped by a formatter 30 into a waveform necessary for testing, thereafter being applied to a memory under test 60. The memory under test 60 is controlled by the control signal CS so that the test data TD is written in the address AD or read out therefrom. The data RD read out of the address AD of the memory under test 60 is fed to a logic comparator 40, wherein it is compared with the expectation data ED from the pattern generator 20 for a match or mismatch therebetween to determine if the memory under test 60 is defective or nondefective. The mismatch is stored as failure data FD in a failure analysis memory 50 at the corresponding address AD. After the test, the contents of the failure analysis memory 50 are checked to analyze failing addresses of the memory under test 60.
Turning next to FIG. 2, a description will be given of how to use the failure analysis memory 50 in the test of semiconductor memories.
In general, the memory testing apparatus is designed to conduct a memory test in various modes; in one of such test modes, the memory is tested in three steps under test conditions (such as the test cycle or period, timing and the test voltage) of gradually increasing severity and the test results are analyzed for each step. In FIG. 2 there are shown examples of test results obtained on the memory 60 in the respective steps. Assume that the test conditions become more stringent in order of TEST1-TEST2-TEST3. Accordingly, when a certain address fails for the first time under some test conditions, it will also fail in subsequent tests under more stringent conditions. Reference numerals A0 to A7 denote addresses of the memory under test 60 and FD indicates that a mismatch is detected, at the address concerned, between the expectation data ED from the pattern generator 20 and the read-out data RD from the memory 60.
TEST1 indicates that the memory 60 is defective at the address A2. TEST2 indicates that the addresses A2 and A6 are defective, but it cannot be judged from TEST2 alone which address, A2 or A6, failed due to changes in the test conditions. Moreover, it is impossible to judge whether the addresses A2 and A6 are both decided as defective under the test conditions of TEST2. From TEST3 it can be judged that the addresses A2, A6 and A7 are defective, but it cannot be decided, either, which address failed because of having changed the test conditions to those of TEST3. In other words, the test conclusions on the address that failed in the previous test need to be ignored in the next test under severer conditions.
To meet this requirement, it is conventional to test the memory 60 at each stage after clearing the contents of the failure analysis memory 50 and then inhibiting the write therein of the comparison results on the address having failed in the previous test (i.e. inhibiting the logical comparison). To perform this, a failure data storage part and a mask data storage part are provided in the failure analysis memory 50 as described later on; upon completion of the test at each stage, failure data FD detected and written in the failure data storage part in the failure analysis memory 50 at that stage is written in the mask data storage part, inhibiting the logical comparison in the next test at the address for which the failure data has been wr
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English-language translation of International Search Report for Patent Application No. PCT/JP/97/03928.
Sato Shin-ya
Tabata Makoto
Advantest Corporation
Cady Albert De
Lamarre Guy
Lathrop David N.
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