Decoupled clocking in testing architecture and method of...

Details Decoupled clocking in testing architecture and method of... Decoupled clocking in testing architecture and method of...

2011-03-29

2011-03-29

Trimmings, John P (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S025000, C714S030000, C714S032000, C714S724000, C714S726000, C714S727000, C714S729000, C714S744000, C714S742000, C714S733000, C714S734000, C702S118000, C702S117000, C702S120000

Reexamination Certificate

active

07917823

ABSTRACT:
A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.

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