Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate
2002-12-30
2004-11-16
Le, Don (Department: 2819)
Electronic digital logic circuitry
With test facilitating feature
C326S105000, C365S201000
Reexamination Certificate
active
06819134
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates to a decoding circuit for a wafer burn-in test, and in particular to a decoding circuit for a wafer burn-in test that internally generates a strobe signal by using external input address signals for the wafer burn-in test.
2. Description of the Related Art
A conventional decoding circuit for a wafer burn-in test receives a strobe address signal for generating a strobe signal and a plurality of input address signals for controlling a decoding operation in the wafer burn-in test. The number of input pins required on a conventional decoding circuit corresponds to the sum of the number of the strobe address signals and the number of the input address signals. Accordingly, as the number of input addresses increase, the area for the input pad containing the input pins also increases, thereby increasing the whole layout area of a semiconductor memory device. In consideration of the relatively large area of the input pad in a typical semiconductor memory device, the number of decoding circuit input pads must be decreased in order to reduce the whole layout area.
Referring to
FIG. 1
, a conventional decoding circuit for a wafer burn-in test is illustrated. As described, the conventional decoding circuit for the wafer burn-in test includes an address control unit
10
, a strobe signal generating unit
20
and a decoding unit
30
.
In general, the address control unit
10
logically operates external input address signals ADD<
8
>, ADD<
9
>, ADD<
11
> and ADD<
12
> and a test signal WBI, and generates address signals AWB<
8
>, AWB<
9
>, AWB<
11
> and AWB<
12
>. In addition, the address control unit
10
buffers the address signals AWB<
9
>, AWB<
11
> and AWB<
12
>, and generates address signals AWD<
9
>, AWD<
11
> and AWD<
12
>.
The strobe signal generating unit
20
receives the strobe address signal AWB<
8
>, and generates a strobe signal VCMDP.
The decoding unit
30
receives the address signals AWBD<
9
>, AWD<
9
>, AWBD<
11
>, AWD<
11
>, AWBD<
12
> and AWD<
12
> from the address control unit
10
and the strobe signal VCMDP from the strobe signal generating unit
20
, and decodes the received signals. In addition, the decoding unit
30
selectively outputs an all word line driving signal ALL, an even word line driving signal EVEN, an odd word line driving signal ODD, word line driving signals
2
RBE and
2
RBO and a sense amp driving signal SAE according to the decoding result.
In detail, the address control unit
10
includes NOR gates NOR
1
-NOR
4
for respectively NORing the strobe address signal ADD<
8
>, the input address signals ADD<
9
>, ADD<
11
> and ADD<
12
>, and the test signal WBI. Inverters IV
1
-IV
4
delay and logically non-reverse the output from the NOR gate NOR
1
and output the address signal AWB<
8
>. Inverters IV
5
-IV
8
delay and logically non-reverse the output from the NOR gate NOR
2
and output the address signal AWB<
9
>. Inverters IV
9
-IV
12
delay and logically non-reverse the output from the NOR gate NOR
3
and output the address signal AWB<
11
>. Inverters IV
13
-IV
16
delay and logically non-reverse the output from the NOR gate NOR
4
and output the address signal AWB<
12
>. Inverters IV
17
-IV
19
delay and logically non-reverse the address signal AWB<
9
> and output the address signal AWD<
9
>. Inverters IV
20
-IV
22
delay and logically non-reverse the address signal AWB<
11
> and output the address signal AWD<
11
>. Inverters IV
23
-IV
25
delay and logically non-reverse the address signal AWB<
12
> and output the address signal AWD<
12
>.
The strobe signal generating unit
20
includes inverters IV
26
-IV
32
for delaying and logically non-reversing the address signal AWB<
8
>, and inverters IV
33
-IV
37
for delaying and logically non-reversing the output from the inverter IV
32
. A NAND gate ND
1
NANDs the output from the inverter IV
32
and the output from the inverter IV
37
. A NAND gate ND
2
NANDs the output from the NAND gate ND
1
and an inputted power up signal PWRUP, and outputs the strobe signal VCMDP.
Finally, the decoding unit
30
includes NAND gates ND
3
-ND
10
for respectively NANDing the address signals AWBD<
9
>, AWD<
9
>, AWBD<
11
>, AWD<
11
>, AWBD<
12
> and AWD<
12
> from the address control unit
10
, and inverters IV
38
-IV
45
for respectively inverting the outputs from the NAND gates ND
3
-ND
10
. NAND gates ND
11
-ND
18
respectively NANDs the outputs from the inverters IV
38
-IV
45
and the strobe signal VCMDP from the strobe signal generating unit
20
. An NMOS transistor N
1
receives the power up signal PWRUP inverted by an inverter IV
46
, and outputs a ground voltage VSS to NAND gates ND
19
-ND
32
composed of a latch. Inverters IV
47
-IV
60
respectively delay the outputs from the NAND gates ND
19
-ND
32
, and output the all word line driving signal ALL, the even word line driving signal EVEN, the odd word line driving signal ODD, the word line driving signals
2
RBE and
2
RBO and the sense amp driving signal SAE.
The conventional decoding circuit for the wafer burn-in test includes the strobe address signal ADD<
8
> as a first address group for generating the strobe signal VCMDP during the wafer burn-in test, and the input address signals ADD<
9
>, ADD<
11
> and ADD<
12
> as a second address group for selectively enabling the word line driving signals during the wafer burn-in test.
Referring now to
FIG. 2
, an operational timing view of the conventional decoding circuit for the wafer burn-in test is shown. When the test signal WBI is enabled during the wafer burn-in test, the strobe address signal ADD<
8
> is enabled, and then the strobe signal VCMDP is generated. When the strobe signal VCMDP is generated from the strobe signal generating unit
20
, the decoding unit
30
decodes the address signals AWBD<
9
>, AWD<
9
>, AWBD<
11
>, AWD<
11
>, AWBD<
12
> and AWD<
12
> from the address control unit
10
. In addition, while the input address signals ADD<
9
>, ADD<
11
> and ADD<
12
> are simultaneously enabled in a high level, a reset pulse RESETBP is generated at the point when the strobe signal VCMDP is generated.
However, the conventional decoding circuit for the wafer burn-in test needs the strobe address signal ADD<
8
> for generating the strobe signal VCMDP and the plurality of input address signals ADD<
9
>, ADD<
11
> and ADD<
12
> to perform the wafer burn-in test. Accordingly, the conventional decoding circuit for the wafer burn-in test requires a special pad for receiving the strobe address signal add<
8
>ADD<
8
> of controlling generation of the strobe signal VCMDP as well as a pad for receiving the external input address signals ADD<
9
>, ADD<
11
> and ADD<
12
>. As a result, the area of the input pads is increased according to the number of pad is increased and thus the whole layout area of the semiconductor memory device is also increased.
SUMMARY OF THE DISCLOSURE
A decoding circuit for a wafer burn-in test may include: an address control unit for buffering a plurality of externally inputted address signals and generating a plurality of internal address signals in order to selectively enable word line driving signals during the wafer burn-in test; a strobe signal generating unit for generating a plurality of delay pulse signals having a predetermined pulse width according to the plurality of address signals, and generating a strobe signal by logically operating the plurality of delay pulse signals wherein each delay pulse signal is enabled when its corresponding address signal inputted externally is transited, and the strobe signal has a pulse when at least one delay pulse signal is enabled; and a decoding unit for decoding the plurality of internal addr
Hynix / Semiconductor Inc.
Le Don
Marshall & Gerstein & Borun LLP
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