Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1993-10-06
1995-05-30
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
365203, 365204, 3652257, G11C 700
Patent
active
054208211
ABSTRACT:
A high-speed decoder for salvaging defective memory cells which has voltage generators VG0 and VG3 for generating voltages having binary logic levels corresponding to the bit information of each column of the addresses of defective memory cells. Upon input of a memory address signal, the voltage level of the bits of each column of the address signal are checked against the voltage levels corresponding to each column from the voltage generator. When all of the columns agree, an address agreement signal is generated by an address corroboration circuit including exclusive OR gates EX0 to EX3 and a NAND gate 10. The output terminals QE0 to QE3 of the voltage generators VG0 to VG3 are connected to the input terminals of the exclusive OR gates EX0 to EX3, and the address input terminals IN0 to IN3 are connected to the other input terminals of the exclusive OR gates EX0 to EX3, and the output terminals of the exclusive OR gates EX0 to EX3 are connected to the input terminal of the NAND gate 10, and the output terminal of the NAND gate 10 is connected to the input terminal of the NAND gate 12 via an inverter 14, and the output terminal QEa of the voltage generator VGa is connected to the other input terminal of the NAND gate 12 via an inverter 15. The fuses F0 to F3 of the voltage generators VG0 to VG3 are selectively burnt in accordance with the value of the set address, and the fuse Fa of the voltage generator VGa is burnt when the optional address is set.
REFERENCES:
patent: 4441170 (1984-04-01), Folmsbee et al.
patent: 4571707 (1986-02-01), Watanabe
patent: 4592024 (1986-05-01), Sakai et al.
patent: 4803656 (1988-02-01), Takemae
patent: 4975881 (1990-12-01), Kagami
Burton Dana L.
Dinh Son
Donaldson Richard
Kesterson James C.
Popek Joseph A.
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