Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1980-06-02
1982-11-23
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365203, G11C 1300
Patent
active
043609015
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention pertains to electronic logic circuits and in particular to such a circuit which is used as a decoder in a semiconductor memory.
BACKGROUND ART
In semiconductor memories an address for a memory cell is received as bi-level signals on a plurality of address lines. These binary address signals must be decoded in order to access a particular row and a particular column within the memory. A decoder is functionally a NOR circuit which generates an output on a selected row or column line with the address signal providing the inputs to the NOR circuit Various control signals are frequently applied to control the NOR circuit so that the proper address signals are received and the output is sequenced to occur at the proper time.
The decoder circuits heretofore used in semiconductor memories have functional adequately for relatively small memory sizes which operate at moderate speeds and powers. But new circuit techniques such as sharing both row and column addresses on the same lines and transmitting these to a row decoder at different times together with bootstrapping of a selected row line above the supply voltage have added new constraints to the design of a row decoder.
DISCLOSURE OF THE INVENTION
A row decoder circuit is disclosed which charges a row line in a semiconductor memory where the row line is selected by a multi-bit memory address. The decoder circuit includes a dynamic OR gate having a plurality of input terminals and an output terminal. Each of the input terminals is connected to receive a respective bit of the address. The input terminal of a dynamic inverter is connected to the output terminal of the OR gate. A row driver transistor is connected to the output terminal of the inverter and to the row line. The voltage state on the output terminal of the inverter determines the conductivity of the row driver transistor which supplies a row enable signal to the row line.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic illustration of a decoder circuit heretofore used in semiconductor memories;
FIG. 2 is a illustration of various control signals which drive the decoder NOR circuits described herein;
FIG. 3 is a schematic illustration of the decoder circuit of the present invention; and
FIG. 4 is a schematic illustration of an alternative embodiment of the decoder circuit of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
A typical decoder circuit as heretofore used in semiconductor memories is illustrated in FIG. 1. Decoder circuit 10 has a plurality of input address lines including 12-20. Address bits A.sub.0, A.sub.1, A.sub.2, A.sub.3 and A.sub.4 are transmitted respectively through the address lines 12-20. Each separate decoder circuit has its unique combination of true and complement address bits, with either the true or complement of each address bit going to each decoder. A particular memory address for a row or column line is a collection of high and low voltage levels on the address lines. The address lines 12-20 are connected respectively to the gate terminal of input transistors 23-30. The drain terminals of each of the input transistors is connected to a common node 32 and the source terminals of each of the input transistors is connected to a common node 34 which serves as the circuit ground. The power for circuit 10 is supplied through a power terminal 36 which is connected to the supply voltage V.sub.cc The voltage V.sub.cc is typically 5.0 volts.
Circuit 10 includes a transistor 38 which has the drain terminal thereof connected to power terminal 36 for receiving voltage V.sub.cc. The source terminal of transistor 38 is connected to node 32. The gate terminal of transistor 38 is connected to receive a precharge signal which is illustrated in FIG. 2.
Circuit 10 further includes a transistor 40 which has the drain and sourc
REFERENCES:
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4081701 (1978-03-01), White et al.
patent: 4082966 (1978-04-01), Lou
patent: 4156938 (1979-05-01), Proebsting et al.
Fears Terrell W.
Mostek Corporation
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