Decoder circuit

Details Decoder circuit Decoder circuit

1981-02-06

1983-01-18

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, G11C 1140

Patent

active

043695035

ABSTRACT:
A decoder circuit which receives a plurality of address signals and selects one of the n.times.m word lines for driving a semiconductor memory device. The decoder circuit includes a high level selection circuit which receives the upper address signals and produces n outputs, one of the n outputs is selected to be a high level, while the other (n-1) outputs are rendered at a low level. The decoder circuit also includes a low level selection circuit which receives the lower address signals and produces m outputs, one of the m outputs is selected to be the low level, while the other (m-1) outputs are rendered at the high level. The decoder circuit additionally includes n.times.m coupling circuits each of which receives one output from the high level selection circuit and one output from the low level selection circuit and which corresponds to one of the n.times.m word lines. Each of the coupling circuit selects the corresponding word line when the high level output from the high level selection circuit and the low level output from the low level selection circuit are simultaneously applied to the coupling circuit.

REFERENCES:
patent: 3736574 (1973-05-01), Gersbach
patent: 4007451 (1977-02-01), Heuber et al.
patent: 4027285 (1977-05-01), Millhoilan et al.
Intel Corp. Bipolar LSI Memory 3102, 3202, "Partially Decoded Random Access 256 Bit Bipolar Memory (3102) and Binary Decoder Drives (3202)", Dec. 1970.
IEEE International Solid-State Circuits Conference, "High Density Memories", Quinn et al., Feb. 16, 1978, pp. 154-155.
IEEE Journal of Solid-State Circuits, "A Fast 7.5 NS Access 1K Bit Ram for Catch-Memory Systems", Kawarada et al., Oct. 1978, vol. SC-13, No. 5, pp. 656-663.
IEEE Transactions on Electron Devices, "Special Issue on Semiconductor Memory", Jun. 1979, vol. ED-26, No. 6, pp. 891-886.
IEEE Journal of Solid State Circuits, "ECL Look-Compatible 1024x4 Bit Ram W/15 NS Access Time", by Glock et al., vol. SC-14, Oct. 1979, No. 5, pp. 850-854.
IEEE Journal of Solid-State Circuits, "A High Speed ECL Look Compatable 64x4 Bit Ram w/bns Access Time", by Ernst et al., vol. SC-15, Jun. 1980, No. 3, pp. 306-310.

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