Decoder and latching circuit with differential outputs

Details Decoder and latching circuit with differential outputs Decoder and latching circuit with differential outputs

1993-04-05

1994-12-13

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326122, H03K 190948, H03K 19096

Patent

active

053732030

ABSTRACT:
A configurable decode circuit (11) having a plurality of inputs (12), a clock input (13), an output (14), and an output (16) is described. The configurable decode circuit (11) is a nor type decoder configurable to different address widths. A latch (17) stores the decode results. A bias circuit (29) enables the configurable decode circuit (11) starting a decode cycle. A differential input stage is coupled between the latch (17) and bias circuit (29). One side of the differential input stage comprises a plurality of transistors (23) coupled in parallel. Each control electrode of the plurality of transistors (23) is coupled to a respective input of inputs (12). The other side of the differential input stage comprises a transistor (28) coupled between the latch (17) and the bias circuit (29). A control electrode of the transistor (28) is coupled to common first electrodes of the plurality of transistors (23).

REFERENCES:
patent: 4825104 (1989-04-01), Yamakoshi et al.
patent: 5237217 (1993-08-01), Hasegawa et al.
patent: 5291076 (1994-03-01), Bridges et al.

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