Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
1998-03-26
2001-08-21
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C712S228000, C712S229000
Reexamination Certificate
active
06279104
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data parallel processing apparatus for processing data with a plurality of processor elements. More particularly, the present invention relates to a debugging system for a parallel processed program that drives the processing apparatus and a debugging method thereof.
2. Description of the Related Art
In a scientific and engineering parallel computer that repeats the same calculating process or the calculations with varied parameters, a data parallel process of which the calculating process is divided by a plurality of processors is performed. In the data parallel processing apparatus, since the same calculation program is executed by a plurality of processor elements in parallel, they perform respective calculating processes with respective data and variables so as to accomplish a high speed calculating process.
On the other hand, in the final stage of software development, a debugging process for checking out source code, executable format, and so forth and for finding errors of a program and of data, and variables, in the program is essential. Conventionally, the debugging process is performed by, for example, the following debugger.
The debugger debugs programs of individual processor units. This type of debugger is referred to as a sequential debugger. The sequential debugger debugs only a process program in one processor element. The debugger tracks the operation of a program of each processor element, stops for example a source program at a particular line, then checks out data and content of variables.
However, when a program for the data parallel processing apparatus with a plurality of processor elements connected in parallel is debugged, a complicated debugging process should be performed for each processor element. Thus, the debugging process is ineffective and thereby takes a long time.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a debugging system for effectively performing a debugging process for a parallel processed program of a data parallel processing apparatus, and thereby largely contributing supporting program development as an effective debugging tool of a parallel processed program and a debugging method thereof.
The present invention is accomplished by a debugging system for use with a data parallel processing apparatus having a plurality of processor element for processing the same process in parallel, the debugging system comprising a plurality of sequential debuggers for debugging process programs of the processor elements, and a management processor for outputting a debug command to the sequential debuggers, causing the sequential debuggers to debug the process programs, receiving reply information therefrom as the debugged results, and managing a debugging process for the data parallel processing apparatus.
The plurality of processor elements (sometimes referred to as PEs) process the same program in parallel. For example, the processor elements process a parallel program in the scientific and engineering calculating process. Each processor element can access a shared memory shared by each processor element along with a dedicated local memory therof. For example, each processor can access the shared memory along with a relevant dedicated local memory.
Each sequential debugger debugs only a program process of a relevant processor element. The sequential debugger performs a debugging process corresponding to a debug command that is received from the management processor. Examples of the debug command are “PRINT” command, “BREAK” command, “CONTINUE” command, “STEP” command, and “P.STAT” command.
In addition, the management processor outputs a debug command to each processor element. The sequential debugger of each processor element debugs the process program corresponding to each processor element. The management processor receives reply information from each processor element as a result of the debugging process for data of the relevant processor element.
Thus, the management processor outputs various debug commands to the sequential debuggers of the individual processor elements and receives reply information from the sequential debuggers. Consequently, the management processor can obtain the statuses of the programs of all the processor elements and effectively manage the debugging process. Thus, the management processor can effectively perform the debugging process.
These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of a best mode embodiment thereof, as illustrated in the accompanying drawings.
REFERENCES:
patent: 5179702 (1993-01-01), Spix et al.
patent: 5325530 (1994-06-01), Mohrmann
patent: 5640500 (1997-06-01), Taylor
patent: 5687375 (1997-11-01), Schwiegelshohn
patent: 5745760 (1998-04-01), Kawamura et al.
patent: 5963746 (1999-10-01), Barker et al.
Murayama Norihisa
Sato Yuji
Elmore Reba I.
Fujitsu Limited
Staas & Halsey , LLP
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