Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-04-02
2000-06-06
Moise, Emmanuel L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714735, 714736, 702 67, G01R 3128
Patent
active
060732644
ABSTRACT:
The present invention discloses a debug tool to provide a test vector to a device under test. The debug tool comprises: (1) a pattern generator unit coupled to the device under test to transmit the test vector to the device under test and to generate a master triggering signal; (2) a waveform acquisition unit coupled to the device under test to receive a first test output from the device under test, the first test output being generated by the device under test in response to the transmitted test vector; and (3) a trigger unit coupled to the pattern generator unit, the waveform acquisition unit, and the device under test to synchronize the pattern generator unit, the waveform acquisition unit, and the device under test.
REFERENCES:
patent: 5289116 (1994-02-01), Kurita et al.
patent: 5412662 (1995-05-01), Honma et al.
patent: 5463639 (1995-10-01), Koishi et al.
patent: 5508607 (1996-04-01), Gibson
patent: 5731984 (1998-03-01), Ullmann
patent: 5854804 (1998-12-01), Winer et al.
Clark Richard F.
Nelson Mark B.
Watrobski Ken R.
Intel Corporation
Moise Emmanuel L.
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