Debug interface including data steering between a processor, an

Details Debug interface including data steering between a processor, an Debug interface including data steering between a processor, an

1998-03-04

2000-11-07

Chaki, Kakali

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

39550044, 714 27, 714 30, 714 31, 714 37, 714 5, G06F 945

Patent

active

061426830

ABSTRACT:
A system for debugging a processor includes a data steering circuit for steering commands and data from a debug port and a parallel input/output port. The data steering circuit also directs commands and data to from the debug port and the parallel input/output port to the same set of debug registers. The data steering circuit also selectively directs trace information indicative of execution of instructions in the processor to either a trace buffer or directly out to a port, such as the debug port or the parallel input/output port.

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