De-fluorination after via etch to preserve passivation

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S624000, C438S725000, C257SE21252, C257SE21311, C257SE21574

Reexamination Certificate

active

10904432

ABSTRACT:
Novel interconnect structures possessing a dense OSG material for 90 nm and beyond BEOL technologies in which a low power density oxygen-based de-fluorination plasma process is utilized to increase NBLoK selectivity are presented. These BEOL interconnect structures are capable of delivering enhanced reliability and performance due to the reduced risk of Cu exposure and hence electromigration and stress migration related failures. The oxygen based de-fluorination process is such that the plasma conditions employed {low power density (<0.3 Wcm−2); relatively high pressure (>100 mT); negligible ion current to wafer surface (applied source frequency only)} facilitate a physical expulsion of residual fluorine present on the chamber walls, wafer surface, and within the via structure; thus, minimizing the extent of NBLoK etching that can occur subsequent to removing polymeric byproducts of via etching.

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