DDR to SDR conversion that decodes read and write accesses...

Details DDR to SDR conversion that decodes read and write accesses... DDR to SDR conversion that decodes read and write accesses...

2005-11-29

2005-11-29

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C365S233100, C711S167000

Reexamination Certificate

active

06971039

ABSTRACT:
A memory module is described which, externally, has the functionality of DDR SDRAMs and contains two groups of conventional SDRAMs. A conversion device provides for the conversion of clock signals, commands, and data. The conversion device contains a changeover switch, a delay locked loop and buffer memory for addresses and commands and also for the data, which are driven in a suitable manner by the delay locked loop.

REFERENCES:
patent: 5971923 (1999-10-01), Finger
patent: 6134180 (2000-10-01), Kim et al.
patent: 6446158 (2002-09-01), Karabatsos
patent: 6507888 (2003-01-01), Wu et al.
Ikeda, H.: “High-Speed DRAM Architecture Development”, IEEE, vol. 34, No. 5, May 1999, pp. 685-692.
“DDR SDRAM Functionality and Controller Read Data Capture”, Micron Technology Inc., vol. 8, Issue 3, pp. 1-24.

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