DDR control

Details DDR control DDR control

2007-10-26

2010-12-07

Elamin, Abdelmoniem (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C711S105000, C711S158000, C365S230040, C365S230080, C365S233130, C710S244000

Reexamination Certificate

active

07849345

ABSTRACT:
A computer system for writing data to a memory is disclosed. The memory controller in the computer system comprises a system clock, which is generated by the memory controller. A first register captures the lower data word based on the rising edge of the system clock. A second register, coupled to the first register, captures the output of the first register based on the rising edge of the system clock. A third register, captures the upper data word based on the falling edge of the system clock. A forth register, coupled to the third register, captures the output of the third register based on the falling edge of the system clock. A first multiplexer is coupled to a forth register and a second register. A delay element, coupled to the system clock and a first multiplexer, adjusts the phase of the system clock. A second multiplexer, coupled to the system clock, generates a data strobe.

REFERENCES:
patent: 7302532 (2007-11-01), Sandorfi
patent: 7464231 (2008-12-01), Raad
patent: 7634623 (2009-12-01), Raad
patent: 2004/0160384 (2004-08-01), Jeffrey et al.
patent: 2005/0050289 (2005-03-01), Raad
patent: 2005/0097392 (2005-05-01), Sandorfi
patent: 2007/0300096 (2007-12-01), Berry et al.

Affiliated with

Also associated with

Rating

DDR control does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DDR control, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DDR control will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4155237