DDR clocking

Details DDR clocking DDR clocking

2007-01-30

2007-01-30

Butler, Dennis M. (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S503000

Reexamination Certificate

active

10641706

ABSTRACT:
A sampling device includes a first delay circuit and a second delay circuit in a parallel configuration, where the first delay circuit and the second delay circuit are responsive to a clock signal. A data sampling circuit may use an output of the first delay circuit and an output of the second delay circuit to sample a data signal synchronized with the clock signal. The data signal and the clock signal may be synchronized according to a double data rate (DDR) protocol.

REFERENCES:
patent: 6466075 (2002-10-01), Douchi et al.
patent: 6510095 (2003-01-01), Matsuzaki et al.
patent: 6510503 (2003-01-01), Gillingham et al.
patent: 6525988 (2003-02-01), Ryu et al.
patent: 6529993 (2003-03-01), Rogers et al.
patent: 6704881 (2004-03-01), Li et al.
patent: 2002/0089359 (2002-07-01), Friedman et al.
patent: 2002/0157031 (2002-10-01), Lin

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