Databus architecture for accelerated column access in RAM

Details Databus architecture for accelerated column access in RAM Databus architecture for accelerated column access in RAM

1993-12-10

1995-05-16

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Precharge

36518901, 365205, 365149, 365190, G11C 700

Patent

active

054167434

ABSTRACT:
The present invention relates to a method of writing or reading a semiconductor random access memory (DRAM or SRAM) having plural sense amplifiers connected to lines and having data bus read and write amplifiers, comprised of providing a pair of data buses for access by each sense amplifier and each read and write amplifier, reading or writing one data bus while precharging the other data bus during a first read or write cycle, and reading or writing the other data bus while precharging the first data bus in a second read or write cycle following the first read or write cycle.

REFERENCES:
patent: 5193075 (1993-03-01), Hatano
patent: 5251175 (1993-10-01), Taguchi
patent: 5293563 (1994-03-01), Ohta

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