Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-04-28
2003-09-02
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C707S793000, C703S001000, C703S014000, C700S097000, C326S038000, C326S039000
Reexamination Certificate
active
06615389
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a database for use in the design of an integrated circuit device and to a design method using such a database. More particularly, the present invention relates to techniques of optimizing a test strategy taken to detect faults, for example, in the integrated circuit device.
A semiconductor device for an electronic unit has been fabricated until just recently by forming individual types of LSIs such as memories and processors on respective semiconductor chips and then mounting and interconnecting all of these chips together on a motherboard like a printed wiring board.
Over the past few years, however, a semiconductor device is increasingly required to reduce its overall size, power dissipation and fabrication cost to further broaden the industrial applicability of an electronic unit including the device. Among other things, a consumer electronic appliance for use in digital information processing has to meet all of these requirements more perfectly than any other electronic unit. Responsive to such a demand from the electronics industry, the prime target of semiconductor technology is now shifting from memories to system LSIs.
Specifically, a system LSI is a single-chip implementation including memories and various types of logic circuits that are integrated together on a single chip. To realize a system-on-chip, not only the process technology of forming devices, like transistors, with dissimilar structures on a common substrate, but also the design technology thereof should be greatly innovated.
Thus, according to a suggested technique of designing a system-on-chip, a database is prepared in advance to design an arbitrary block consisting of a great number of cells, which together implement a required function, e.g., a so-called “functional block”. By using such a database, any desired system LSI can be designed as a combination of these blocks. In such a case, a specific physical structure for executing an intended function has been defined in advance for each functional block. Thus, in the physical design of an overall semiconductor device, only the interconnections among these functional blocks and peripheral circuitry have to be newly laid out. In this manner, the conventional method tries to increase the design efficiency considerably.
In the conventional design process, however, a core has been selected in compliance with various requirements and specifications that should be met to realize a desired function, and has been designed simply by following a test procedure specified for the core. That is to say, an overall integrated circuit is designed as a collection of those cores in accordance with such an overly simplified procedure. In other words, when such a technique is adopted, a test cost is automatically determined as a result of the design process and it has been difficult to reduce the test cost while maintaining desirable test quality. Also, a core has not been selected and designed in such a manner as to minimize the cost of testing an overall semiconductor integrated circuit device.
SUMMARY OF THE INVENTION
An object of the present invention is reducing the cost of carrying out a test, like fault detection diagnosis, on an integrated circuit device that is being designed using a database, in which data about various components is stored as a collection of virtual cores in a flexibly usable state.
A first inventive database for designing an integrated circuit device includes multiple cores for storing thereon data needed in designing the device. In the first database, the cores are associated with the same function and mutually different test techniques.
A core associated with a test technique that would be advantageous in terms of a particular parameter can be selected from the inventive database. Thus, a strategy for a test, like fault detection diagnosis, for example, can be optimized in an integrated circuit device.
A second inventive database for designing an integrated circuit device also includes multiple cores for storing thereon data needed in designing the device. In the second database, at least one test technique is stored for each said core.
If such a database is used, a test cost required for each core can be estimated in association with a particular parameter. Thus, it is possible to select an optimum test strategy for detecting faults, for example, in an integrated circuit device.
In one embodiment of the present invention, information about a test cost, which is required by the at least one test technique for each said core, is stored.
In such an embodiment, a test technique that would be advantageous in terms of a test cost can be selected from the inventive database. Thus, the strategy for a test, like fault detection diagnosis, on an integrated circuit device can be optimized about the test cost.
In this particular embodiment, the information about the test cost is at least one item selected from the group consisting of: how many pins should be controlled and monitored externally when the core is tested; how long a test pattern is; how much the integrated circuit device increases its area when a test circuit is added; fault coverage; test time; number of design process steps; and yield of the device.
A third inventive database for designing an integrated circuit device includes at least one core for storing thereon data needed in designing the device. In the inventive database, information about a test constraint is stored for a technique of testing the at least one core.
By using such a database, an optimum test technique for detecting faults in an integrated circuit device, for example, can be selected so as to meet a test constraint.
In one embodiment of the present invention, the information about the test constraint is at least one item selected from the group consisting of: in what state a pin should be to control the core in a test mode or to keep the core safe and non-broken; whether the core should be dynamic or static; whether or not a test pattern may be divided; and where the test pattern should be divided.
A first inventive method for designing an integrated circuit device uses a core database. The core database includes multiple cores for storing thereon data needed in designing the device. A plurality of test techniques are stored for the respective cores. The method includes the steps of: a) picking candidate cores and associated test techniques for use in testing the device from the database; b) estimating a total test cost for each said core and associated test technique picked; and c) selecting one of the candidate cores and associated one of the test techniques that will minimize the test cost.
According to the first method, an integrated circuit device can be tested under such conditions as minimizing the test cost. Thus, an optimum strategy can be selected for detecting faults in the device, for example.
In one embodiment of the present invention, the estimated test costs are presented in the step b). A process for minimizing the test cost can be performed rapidly by doing so.
In another embodiment of the present invention, it is determined in the step b) whether or not each said test technique picked meets a constraint on the number of pins available for testing, and the test costs are estimated for only the test techniques meeting the constraint. In this manner, inappropriate test techniques are not picked.
In this particular embodiment, if one of the test techniques picked fails to comply with the constraint, an error is preferably indicated in the step b).
In still another embodiment, a test pattern for each said core picked is divided in the step b) with respect to time so as to meet a constraint on the number of pins available for testing, the test pattern is modified to minimize a test time and then the test cost is estimated. In this manner, a cost associated with a test time can be estimated more accurately.
In yet another embodiment, the test cost is estimated in the step b) by weighting priority orders in terms of a parameter affectin
Ichikawa Osamu
Ohta Mitsuyasu
Takeoka Sadami
Rossoshek Helen B
Siek Vuthe
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