Data transmission system and data transmission apparatus

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses

Reexamination Certificate

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Details

C713S503000, C709S208000, C709S253000

Reexamination Certificate

active

07620837

ABSTRACT:
A data transmission system including a slave device (30) and a master device (10) is disclosed. Slave device (30) may include a slave side clock signal generator section (32) for generating a slave side clock signal (CLKSOUT), a phase adjusting circuit (40) for controlling a phase of a slave side clock signal (CLKSOUT), output sections (33-1to33-m) for outputting transmission data signals (SD1to SDm) in response to slave side clock signal (CLKSOUT), and a timing reference signal generator section (34) for outputting a timing reference signal (SSPH) in response to slave side clock signal (CLKSOUT). Master device (10) may include a master side clock signal generator section (11) for generating master side clock signal (CLKM), input sections (12-1to12-m) for sampling data signals (SD1to SDm) in response to master side clock signal (CLKM), and a phase compare circuit (19) for generating a phase adjustment instruction signal (SADJOUT) based upon timing reference signal (SSPH) and master side clock signal (CLKM). Phase adjusting circuit (40) may adjust a phase of slave side clock signal (CLKSOUT) in response to phase adjustment instruction signal (SADJOUT). In this way, data setup and/or hold times may be improved.

REFERENCES:
patent: 5864592 (1999-01-01), Itri
patent: 6078623 (2000-06-01), Isobe et al.
patent: 6329858 (2001-12-01), Sobue
patent: 6385263 (2002-05-01), Bowers et al.
patent: 6839393 (2005-01-01), Sidiropoulos
patent: 2002/0020852 (2002-02-01), Huang
patent: 2002/0116468 (2002-08-01), Ishikawa
U.S. Appl. No. 10/062,907, filed Aug. 22, 2002, Ishikawa, Toru.

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