Data transmission/reception system

Details Data transmission/reception system Data transmission/reception system

2006-03-07

2006-03-07

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S086000, C326S090000, C326S082000

Reexamination Certificate

active

07009426

ABSTRACT:
In the process of transferring a clock signal and a plurality of data signals which are in synchronization with the clock signal, a driving pulse width of a driver switch is feedback-controlled by a clock transmission system (12), whereby the clock signal is transmitted at a small amplitude. A control signal having the pulse width is used for controlling the driver switch in each data transmission system (13), whereby transfer of each data signal at a small amplitude is realized at the same time. Further, in a clock reception system (10), the control signal having the pulse width is used in delay control of a clock delay circuit, whereby an optimum latch timing of received data in each data reception system (11) is realized.

REFERENCES:
patent: 5418478 (1995-05-01), Van Brunt et al.
patent: 5694060 (1997-12-01), Brunt et al.
patent: 6452421 (2002-09-01), Saito
patent: 6775328 (2004-08-01), Segaram
patent: 11-194748 (1999-07-01), None
patent: 2002-94489 (2002-03-01), None
patent: 2002-101076 (2002-04-01), None

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