Data transfer circuit for transferring data between a first...

Details Data transfer circuit for transferring data between a first... Data transfer circuit for transferring data between a first...

2006-03-13

2008-09-23

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S501000, C713S503000

Reexamination Certificate

active

07428654

ABSTRACT:
A data transfer circuit includes a first transfer circuit receiving the first transfer signal, a second transfer circuit receiving the second transfer signal, a third transfer circuit receiving the first transfer signal and an inverted first transfer signal from the first transfer circuit and transferring the first transfer signal in response to a reply signal, a fourth transfer circuit receiving the second transfer signal and an inverted second transfer signal from the second transfer circuit and transferring the second transfer signal in response to the reply signal.

REFERENCES:
patent: 5841298 (1998-11-01), Huang
patent: 6931561 (2005-08-01), Carpenter et al.
patent: 7093144 (2006-08-01), Skroch
patent: 7161999 (2007-01-01), Parikh
patent: 2006/0020836 (2006-01-01), Oikawa
patent: 2004-217873 (2004-08-01), None
W.J. Bainbridge, et al., “Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding”, Proc. Async, Apr. 2001, pp. 118-126.

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