Data transfer circuit and method for a semiconductor memory

Details Data transfer circuit and method for a semiconductor memory Data transfer circuit and method for a semiconductor memory

1998-06-23

2000-10-10

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 96, 326 82, 365233, H03K 1900, H03K 19096

Patent

active

061305588

ABSTRACT:
A circuit and method are described for transferring data in a semiconductor memory in synchronism with a reference clock. A data transfer circuit according to the invention includes a non-overlapping clock generator, a data output circuit, and a data input circuit. The non-overlapping clock generator generates a plurality of non-overlapping clock signals, each of which is active during a different time interval during a period of one external clock cycle. The data output circuit selects and outputs a selected one of a plurality of internal data signals in response to an active one of the non-overlapping clock signals. The data input circuit then receives the selected one of the internal data signals and outputs it to the semiconductor memory in response to the active one of the non-overlapping clock signals. By utilizing a non-overlapping clock generator to produce multiple clock pulses during a single external clock cycle, each of which triggers data transfer, data processing speed and operation rate is improved. Detrimental increase in power consumption, which normally results from an increase in the operation rate within the circuit, is reduced by removing the need for multiple input receivers.

REFERENCES:
patent: 4829485 (1989-05-01), Hatanaka et al.
patent: 5627795 (1997-05-01), Nitta
patent: 5915105 (1999-06-01), Farmwald et al.
patent: 5973520 (1999-10-01), Maruyana
patent: 5995443 (1999-11-01), Farmwald et al.

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