Data transfer circuit

Details Data transfer circuit Data transfer circuit

2001-01-05

2002-01-29

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S230030, C365S189011, C365S149000

Reexamination Certificate

active

06343039

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. 2000-2010 filed on Jan. 7, 2000 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a data transfer circuit, and more particularly, to a data transfer circuit having a configuration capable of preventing erroneous behaviors beforehand, which are caused by a leakage current from non-selected data transfer devices connected to data lines, which is suitable for preventing erroneous behaviors due to a leakage current from data lines of a semiconductor storage device highly integrated and operative with a low voltage.
2. Related Background Art
Regarding semiconductor storage devices, technologies are under continuous progress for higher recording density, or higher integration, and higher operation speed. Along with wider and wider diffusion of portable information terminals, etc., technologies for enabling operation with a low source voltage, as well, are under energetic development.
Under the tendency, semiconductor devices forming semiconductor integrated circuits are now being required to operate at high speeds with low voltages. The most widely employed technique for this purpose is to lower threshold voltages (Vth) of semiconductor devices. That is, by not only lowering source voltages but also lowering threshold voltages of semiconductor devices, which are activation voltages thereof, speed-up of operation is being attempted.
This tendency of lowering the threshold voltage, however, has resulted in increasing a current that flows during off-period of a semiconductor device, that is, off-leakage current. During off period of a semiconductor device, the semiconductor device is supplied with a voltage of a level that should maintain inoperative. However, as a result of a decrease of the threshold voltage of the semiconductor device, even when the current across the device is desired to be zero, a certain level of leakage current (off-leakage current) undesirably flows. This off-leakage current will cause an increase of erroneous behaviors of the semiconductor integrated circuit and the power consumption during off period of the circuit, with a high possibility.
FIG. 1
is a block diagram of a conventional semiconductor storage device. Referring to
FIG. 1
, examples of erroneous behaviors of a semiconductor integrated circuit caused by an off-leakage current will be explained below.
This semiconductor storage device is RAM, including memory cells (RAM cells) CL of n+1 rows and m+1 columns. A horizontally continuous series is called one row, and each word line WL is provided for each row to select the row by applying a signal thereto. A vertically continuous series is called a column, and each data line DL is provided for each column to read/write data. That is, with a signal applied to a word line WL, RAM cells in a corresponding row are selected for reading/writing, and data read out from RAM cells of the row, or data to be written in RAM cells of the row, is transmitted as a signal through a data line DL. Input and output of the data read from the RAM cell, or the data to be written in the RAM cell, are controlled by a write/read circuit WRC to which data lines DL are connected, respectively.
Upon reading/writing data, memory cells in a word line supplied with a non-select signal is expected to be inoperative completely, and they are absolutely disconnected from the data line such that no data signal is transmitted to the data line.
However, with the movement to lower source voltages and lower threshold voltages of semiconductor devices, there is the possibility that an off-leakage current flows in a semiconductor device connecting a data storage portion and a data line in each memory cell even during its off period. That is, since the threshold voltage of the semiconductor device is low, a current, although small, undesirably flows even by application of a non-selection signal. As a result, non-selected memory cells are also transmit data signals to the data line by off-leakage currents, and disturb transfer of a data signal from the selected memory cell to the data line.
Normally, non-selected memory cells are much more than selected memory cells, and if off-leakage currents flow in a number of non-selected memory cells simultaneously, erroneous behaviors of the semiconductor device occur.
This problem will be explained with reference to FIG.
1
.
For example, when a selection signal is applied to the word line WL
0
for the No.
0
row, the expected behavior is that data of the RAM cell CL
00
in the No.
0
row and No.
0
column is transmitted to the data line DL
0
of the No.
0
column. Assume here that the data stored in the RAM cell CL
00
in the No.
0
row and No.
0
column is “1”.
However, if all or almost all of data stored in non-selected memory cells in other rows connected to the data line DL
0
for the No.
0
column, off-leakage currents result in undesirably flowing to a number of non-selected RAM cells from the data line DL
0
. These off-leakage currents are going to transmit data “
0
” to the data line DL
0
, and disturb transmission of the intended data “1” from the selected RAM cell CL
00
in the No.
0
row and No.
0
column.
Then, when these off-leakage currents of the non-selected RAM cells gather and reach a magnitude equivalent to or larger than the current by the behavior of the selected RAM cell, there occurs the error that data “0” is undesirably transmitted to data line DL
0
.
FIG. 2
is a graph that shows a relation between threshold voltage Vth of memory cells, and the cell current and off-leakage current. Assume here that the semiconductor storage device includes bit lines (word lines) for 128 rows.
In this example, when the threshold voltage Vth is 0.4 V or higher, there is the difference of at least 10
2
times between the magnitude of the cell current of one row and the off-leakage current of bit lines of 128 rows, and erroneous operation will not occur.
However, as the threshold voltage Vth decreases to 0.3V and to 0.2V, the magnitude of the cell current of one row and the off-leakage current of bit lines of 128 rows get closer, and when the threshold voltage Vth is around 0.2V, both currents are very close, depending upon process variations of memory cells. If the movement toward lower threshold voltage progresses, the magnitude of the cell current of one row and the magnitude of the off-leakage current of bit lines of 128 rows will become approximately equal, or the magnitude of the off-leakage current of bit lines of 128 rows may become larger.
Although the graph of
FIG. 2
is of a semiconductor storage device by a 0.18 &mgr;m process, it is possible that, in a semiconductor storage device with 256 rows and 256 columns of a 0.07 &mgr;m process generation, the threshold voltage Vth decreases to 0.23 V and the leakage current reaches three times the cell current.
In such cases, data transmission by a cell current of a selected memory cell will be disturbed by the off-leakage current, erroneous data will be transmitted from non-selected memory cells, and the semiconductor storage device will operate erroneously.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a data transfer circuit having a configuration capable of preventing erroneous behaviors beforehand, which are caused by a leakage current of an interface input/output block such as non-selected data transfer devices connected to data lines.
According to the invention, there is provided a data transfer circuit comprising data lines for transferring data, interface input/output blocks connected to the data lines to input or output data through the data lines, and a leakage current monitor/compensate circuit connected to the data lines to monitor and store the magnitude of a leakage current in the data lines before input or output of the data and to ge

Affiliated with

Also associated with

Rating

Data transfer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data transfer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data transfer circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2861023