Electrical computers and digital data processing systems: input/ – Input/output data processing – Concurrent input/output processing and data transfer
Reexamination Certificate
2000-08-31
2004-02-17
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Concurrent input/output processing and data transfer
C710S007000, C710S020000, C710S022000, C710S033000, C710S036000, C709S231000
Reexamination Certificate
active
06694386
ABSTRACT:
This application is based on an application No. 11-250864 filed in Japan, the content of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a data transfer apparatus that relays a signal that needs to be transferred in real-time. In particular, the present invention relates to a technique for controlling the retransmission of data on a transfer path after the data has been relayed.
(2) Description of the Prior Art
Data transfer apparatuses have been developed for relaying ISDN (Integrated Services Digital Network) data which needs to be transferred in real time. Such apparatuses receive the ISDN data once and convert the data to an infrared signal which is transmitted to a peripheral device. When necessary, the retransmission control is performed data to convert the data to an infrared signal for retransmission.
The infrared signals transmitted by such a data transfer apparatus are received by another data transfer apparatus whose construction is a mirror image of the first apparatus. This second data transfer apparatus converts the infrared signal back to ISDN data. In this way, two data transfer apparatuses can be used to form a wireless ISDN data transfer link.
FIG. 1
is a block diagram showing the overall construction of a conventional data transfer apparatus that transfers data in accordance with retransmission control.
As shown in
FIG. 1
, the conventional data transfer apparatus includes an input unit
51
, an ISDN control unit
52
, a calculation unit (hereafter CPU)
53
, an address decoding unit
54
, a memory
55
, and an infrared signal communication unit
56
. The input unit
51
receives an input of ISDN data. The ISDN control unit
52
analyzes and demultiplexes the received ISDN data and converts it into data that can be read by the CPU
53
. The CPU
53
outputs an address signal that specifies one of the ISDN control unit
52
, the memory
55
, and the infrared signal communication unit
56
, together with a read signal or a write signal that is a control signal for performing a data read or a data write. The address decoding unit
54
decodes the address signals outputted by the CPU
53
and generates chip select signals for specifying the units in the data transfer apparatus. The memory
55
is used for data reads and data writes by the CPU
53
. The infrared signal communication unit
56
converts the data in the memory
55
into an infrared signal that it outputs.
Note that the ISDN control unit
52
, the memory
55
, and the infrared signal communication unit
56
are each composed of separate chips.
The infrared signal communication unit
56
includes an output unit
57
for outputting infrared signals to a peripheral device and an input unit
58
for receiving a retransmission request signal that the peripheral device sends as infrared data.
The following describes the operation of each component in the data transfer apparatus described above. This explanation first describes the standard operation and then the operation when data is retransmitted in response to the CPU
53
having received a predetermined retransmission request signal sent by as peripheral device.
FIG. 2
shows the sequence of data inputs and outputs within this conventional data transfer apparatus.
Note that the sequence shown in this drawing also shows the operations performed by the infrared interface of the peripheral device that receives infrared data from the present data transfer apparatus.
During normal operation, the input unit
51
receives an input of ISDN data, which is sent to the ISDN control unit
52
(steps S
11
, S
21
). The ISDN control unit
52
analyzes the ISDN data and demultiplexes it to obtain data that can be read by the CPU
53
. This data is temporarily stored in the registers provided inside the CPU
53
(steps S
12
, S
22
)
In more detail, when data is to be sent from the ISDN control unit
52
to the CPU
53
, the CPU
53
outputs an address signal, which shows the address assigned to the ISDN control unit
52
, to the address bus and a read signal R to the read signal line.
The address decoding unit
54
decodes the address signal and outputs a chip select signal CS_I specifying the ISDN control unit
52
.
The ISDN control unit chip select signal CS_I specifies the ISDN control unit
52
. The read signal R has data read out from the ISDN control unit
52
and transferred to the CPU
53
, where it is temporarily stored in the internal registers.
Next, the data that is temporarily stored in the registers of the CPU
53
is sent to the infrared signal communication unit
56
(steps S
14
, S
24
). The infrared signal communication unit
56
generates infrared data from the received data and has the output unit
57
output an infrared signal in accordance with this infrared data (steps S
15
, S
25
).
A retransmission request signal outputted by the peripheral device us received by the input unit
58
(step S
16
).
The infrared signal communication unit
56
outputs the received retransmission request signal to the CPU
53
(step S
17
).
The data stored in the registers in the CPU
53
is stored in the memory
55
in case a retransmission request is received (step S
13
). When the CPU
53
receives a retransmission request signal, the data stored in the memory
55
is sent via the CPU
53
(step S
18
) to the infrared signal communication unit
56
(step S
19
). The infrared signal communication unit
56
generates infrared data from the received data and has the output unit
57
output an infrared signal in accordance with the infrared data (step S
20
).
In more detail, when data is sent from the CPU
53
to the memory
55
, the CPU
53
first outputs a write signal W and an address signal showing an address that is assigned to the memory
55
.
The address decoding unit
54
decodes the address signal and outputs a chip select signal CS_F that specifies the memory
55
.
This memory chip select signal CS_F specifies the memory
55
, so that the data that is stored in the registers in the CPU
53
is stored in the memory
55
.
When data is sent from the memory
55
to the infrared signal communication unit
56
via the CPU
53
, the CPU
53
outputs a read signal R and an address signal that shows an address assigned to the memory
55
.
The address decoding unit
54
decodes this address signal and outputs a chip select signal CS_F that specifies the memory
55
.
This memory chip select signal CS_F selects the memory
55
, so that data in the memory is read out by the CPU
53
and stored in the internal registers in the CPU
53
.
After this, the CPU
53
outputs a write signal W and an address signal that specifies an address assigned to the infrared signal communication unit
56
.
The address decoding unit
54
decodes this address signal and outputs a chip select signal CS_O that specifies the infrared signal communication unit
56
.
The infrared signal communication unit
56
is specified by this infrared signal communication unit chip select signal CS_O, so that the data stored in the registers of the CPU
53
is written into the infrared signal communication unit
56
where it is processed thereafter.
The procedure described above has data transferred by the output unit
57
using standard infrared signals. This transferred data is based on the ISDN data stored in the memory
55
. By sending a retransmission request signal to the CPU
53
, a peripheral device can have the data in the memory
55
(hereafter “retransmission data”) transferred to the infrared signal communication unit
56
where, in addition to the standard output described above, the output unit
57
outputs an infrared signal based on the retransmission data.
The following describes the retransmission of data in more detail. The retransmission data is transmitted from the memory
55
to the infrared signal communication unit
56
in the same way as during standard data transmission. This means that the CPU
53
first outputs a read signal R and an address signal showing an address that is assigned to the memo
Arase Yoshitaka
Morioka Masaaki
Farooq Mohammad O.
Gaffin Jeffrey
Matsushita Electric - Industrial Co., Ltd.
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