Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1999-10-25
2003-02-04
Lee, Thomas (Department: 2183)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C375S370000, C327S145000
Reexamination Certificate
active
06516420
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to transferring information across an asynchronous interface and, more particularly, to a high-performance, error free data synchronization using a parallel handshake pipeline.
BACKGROUND OF THE INVENTION
System designers are faced with the need to integrate more features and capabilities into a given system and to provide higher performance interfaces between different systems. The need for integrating high performance system features further includes support for synchronous and asynchronous system interfaces. Asynchronous interfaces provide system designers with greater flexibility by relieving them of the strong clocking requirements of a synchronous system. Asynchronous interfaces, however, have many disadvantages such as extra latency for data synchronization and the increased probability of data corruption during data transfer.
Data corruption primarily occurs because of metastability across an asynchronous interface. Metastability has been very well investigated in the past and there are several known solutions. The known solutions have an undesirable trade-off between performance and reliability. In particular, the known solutions are either very good in performance with less immunity to error, or are error-free with poor performance. For example, a first known solution is to provide a full handshake between the transmitting device and the receiving device. The full handshake method, although error free, has a very high latency to transfer data, thereby reducing the performance considerably. Each transaction requires four or more receiver clock cycles to transfer the data. Thus, the full handshake method eliminates the metastability problem and is error free, but has very low performance and is not applicable for high performance designs.
A second known solution utilizes synchronizing latches to sample a data valid signal across an asynchronous interface. The data valid signal passes through the synchronizing latches to reduce the probability of a metastable condition. This second method is useful for high performance applications since data is read on every cycle of the core domain. However, this method still has several potential disadvantages, such as, the same data may be read twice or may be skipped completely because of metastability. Either scenario causes loss of data which may seriously affect system functionality since transaction information is lost in the transfer. This technique is not desired in high performance systems where re-transmission of data comes at a very high cost. This method also suffers from very poor debug capabilities and there is no mechanism to throttle or control the flow of incoming data.
It is therefore desired to provide a system and method for transferring data across an asynchronous interface at a very high throughput for use in high performance systems while also reducing or otherwise eliminating transfer errors. It is also desired to provide throttle control and debug capabilities.
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Jerry M. Rosenberg, “Dictionary of Computers, Information Processing & Telecommunications”, Second Edition, John Wiley & Sons, Inc., 1984, 4 pgs.
Agrawal Ritesh Radheshyam
Audityan Srinath
Stone Chris Randall
Chiu Joanna G.
King Robert L.
Lee Thomas
Motorola Inc.
Trujillo James K.
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