Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2005-03-08
2008-03-25
Suryawanshi, Suresh K (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C365S233100, C375S354000
Reexamination Certificate
active
07350092
ABSTRACT:
A data synchronization arrangement is provided for exchanging clocked data between different clock domains running at the same clock frequency but at an arbitrary relative phase shift. An input data stream synchronized in the first clock domain is written into respective locations of a buffer memory through a write select multiplexer under control of a write select shift register clocked by the first domain clock. An output data stream synchronized in the second clock domain is read from the respective locations of the buffer memory through a real select multiplexer under control of a read select shift register clocked by the second domain clock. A bit synchronization circuit is provided for loading the read select shift register with a bit pattern that has a relative offset relative to the bit pattern of the write select shift register, to correlate for the difference in clock phases.
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Goller Joerg
Reichel Norbert
Brady III Wade J.
Suryawanshi Suresh K
Telecky , Jr. Frederick J.
Texas Instruments Deutschland GmbH
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