Data strobe gating for source synchronous communications...

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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C365S230080, C365S230020

Reexamination Certificate

active

06940760

ABSTRACT:
A circuit arrangement and method are used in connection with a data latch that is coupled to a data source over a source synchronous communications interface to disable the data latch from latching data whenever the data source is not driving the source synchronous data strobe signal. As such, when the data source is not driving the source synchronous data strobe signal, undesired and/or inadvertent latching by the data latch can be avoided. Moreover, in implementations where a data strobe signal line is bidirectional, and capable of being driven either by the data source or by another circuit used to access the data source (e.g., a memory controller), disabling data latching as described herein can minimize the risk of driver damage resulting from conflicting attempts to drive the data strobe signal line at both ends.

REFERENCES:
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patent: 6316980 (2001-11-01), Vogt et al.
patent: 6456544 (2002-09-01), Zumkehr
patent: 6768690 (2004-07-01), Kwon et al.
patent: 6834023 (2004-12-01), Bell et al.
patent: 6850457 (2005-02-01), Cowles et al.
“Double Data Rate (DDR) SDRAM Specification”,JEDEC Standard, JESD79, JEDEC Solid State Technology Association 2000, Arlington, VA, (Jun. 2000).
U.S. Appl. No. 09/617,558, entitled “Programmable Compensated Delay for DDR SDRAM Interface,” filed on Jul. 17, 2000 by Borkenhagen et al. (ROC920000157US1).

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