Data sorting in memories

Details Data sorting in memories Data sorting in memories

2006-03-21

2006-03-21

Mai, Son (Department: 2827)

Static information storage and retrieval

Read/write circuit

Multiplexing

C365S230030, C365S233100, C365S238500

Reexamination Certificate

active

07016235

ABSTRACT:
A sorting circuit (140) transfers data between a first group of at least four lines (134) on which the data items are arranged based on their addresses, and a second group of lines (138, WD0R, WD0F, WD1R, WD1F) on which the data items are arranged based on the order in which they are read or written in a burst operation. Six signals (SORT) and their complements are sufficient to control the sorting circuit for both the read and the write operations, and provide both the DDR and the DDR2 functionality.

REFERENCES:
patent: 6011737 (2000-01-01), Li et al.
patent: 6115321 (2000-09-01), Koelling et al.
patent: 6285578 (2001-09-01), Huang
patent: 6522599 (2003-02-01), Ooishi et al.
patent: 6563747 (2003-05-01), Faue
patent: 6597630 (2003-07-01), Konishi et al.
patent: 6600691 (2003-07-01), Morzano et al.
patent: 6621747 (2003-09-01), Faue
patent: 6687181 (2004-02-01), Usuki et al.
patent: 6775201 (2004-08-01), Lee et al.
patent: 2002/0149960 (2002-10-01), Yoo et al.
patent: 2003/0026161 (2003-02-01), Yamaguchi et al.
patent: 2004/0098551 (2004-05-01), Heo et al.
JEDEC Standard: DDR2 SDRAM Specification: JESD79-2A, Jan. 2004, JEDEC Solid State Technology Association.
Preliminary Data Sheet: 1G bits DDR2 SDRAM: EDE1104AASE (256M words×4 bits): EDE1108AASE (128M words×8bits); Elpida Memory, Inc. 2003.
Davis, Brian; Mudge, Trevor; Jacob, Bruce; Cuppu, Vinodh “DDR2 and Low Latency Variants” Electrical Engineering and Computer Science, University of Michigan, Ann Arbor; Electrical & Computer Engineering, University of Maryland, College Park, pp. 1-15.
HYS64T32000GDL (256 Mbyte): HYS64R64020GDL (512 Mbyte) DDR2 Small Outline DIMM Modules; Data Sheet, vol. 82, Oct. 2003, Infineon Technologies.
Preliminary Data Sheet: 512 M bits DDR SDRAM: EDD5104ABTA (128M words×4 bits): EDD5108ABTA (64M words×8 bits); Elpida Memory, Inc. 2002-2003.
JEDEC Standard: Double Data Rate (DDR) SDRAM Specification: JESD79D, Jan. 2004, JEDEC Solid State Technology Association.

Affiliated with

Also associated with

Rating

Data sorting in memories does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data sorting in memories, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data sorting in memories will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3525025