Data signal output circuit and semiconductor memory device inclu

Details Data signal output circuit and semiconductor memory device inclu Data signal output circuit and semiconductor memory device inclu

1994-12-20

1997-02-04

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518901, 36518907, G11C 700

Patent

active

056005997

ABSTRACT:
An object of the present invention is to improve the output speed of a data signal output circuit having a latch circuit when the supply voltage is low. The data signal output circuit according to the present invention includes a latch circuit; an output circuit; a latch control circuit; an output control circuit; and a supply voltage decrease detection circuit. The latch circuit latches and holds a data signal according to a latch signal output from the latch control circuit. By setting the latch signal to one of two logical states, the latch circuit changes to a through state directly outputting an input data signal. The output circuit changes between a state for outputting a data signal from the latch circuit and a high-impedance state according to an output control signal output from the output control circuit. The supply voltage decrease detection circuit detects whether or not the supply voltage is less than a pre-determined value. When the supply voltage decrease detection circuit detects that the supply voltage is less than the pre-determined value the latch control circuit outputs a latch signal to set the latch circuit to the through state and the output control circuit outputs an output control signal to set the output circuit to output the data signal from the latch circuit.

REFERENCES:
patent: 5311471 (1994-05-01), Matsumoto et al.
patent: 5329506 (1993-08-01), Dachtera et al.
patent: 5384736 (1995-01-01), Jung et al.

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