Data sensing circuit of semiconductor memory

Details Data sensing circuit of semiconductor memory Data sensing circuit of semiconductor memory

2001-07-05

2002-10-29

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S202000, C365S207000

Reexamination Certificate

active

06473348

ABSTRACT:

This application claims priority upon Korean Patent Application No. 200066805, filed Nov. 10, 2000, the contents of which are incorporated by reference herein in their entirety.
FIELD OF THE INVENTION
This invention relates generally to dynamic random access memory devices, and more particularly to a memory cell core circuit that is activated when sensing memory cell data on bitlines.
BACKGROUND OF THE INVENTION
The greater the density of dynamic random access memory (DRAM), the greater the problems relevant to densely packed data transmission lines (e.g., bitlines). In general, an operation for sensing data stored in a memory cell begins by activating a pass transistor that is coupled to a selected wordline. Then, charges are transferred to the bitlines coupled to the memory cell, which is called “charge sharing”. A sense amplifier assigned in the bitline amplifies the voltage difference between the selected bitline and the complement thereof and transfers the signal to an input/output line as an amplified data signal. The data sensing path and memory cell as a unit is a first data sensing circuit, which is called a memory cell core circuit.
FIG. 1
shows a general memory cell core circuit.
As shown in
FIG. 1
, a plurality of memory cells MC are connected to a bitline pair BLi/BLBi (or BLj/BLBj) in which isolation transistor pairs N
1
/N
2
and N
3
/N
4
are disposed therein. A sense amplifier SA is disposed between the isolation transistor pairs N
1
/N
2
and N
3
/N
4
and connected to the bitline pairs BLi/BLBi and BLj/BLBj to which bitline precharge/equalization circuits PQi and PQj, respectively comprising NMOS transistor pairs N
5
/N
6
and N
7
/N
8
, are connected.
A data sensing operation of the memory cell core circuit of
FIG. 1
is now explained with reference to
FIGS. 1 through 3
. Assuming an i
th
block is selected, an isolation signal ISOi applied to gates of the isolation transistor pair N
1
/N
2
in the i
th
block goes high, and an isolation signal ISOj applied to gates of the isolation transistor pair N
3
/N
4
in the j
th
block goes low. The bitlines BLi/BLBi in the i
th
block will be precharged and equalized to a bitline precharge/equalization voltage VBL when equalization signal EQi is brought high. When the equalization is then brought down low, when a wordline WLiO is selected charge sharing between the memory cell MC and bitline BLi is established in response to the data held in the memory cell MC. At that time, the bitline BLBi is precharged up to an initial precharge voltage VBL. The sense amplifier SA amplifies a minute potential difference between bitlines BLi and BLBi in response to a sense amplifier control signal SAE being brought high.
The voltage difference between the bitlines BLi and BLBi generated by the charge sharing is at least capable of inducing a triggering of the sense amplifier SA, in order to accomplish a reliable sense amplification operation of the sense amplifier SA. However, there is mutual capacitance (or coupling capacitance) because the bitline pair BLi/BLBi being activated are parallel and spaced closely enough together on the semiconductor wafer to establish capacitance between them. Assuming that a selected memory cell stores a logical “1” bit data and the voltage rise from the primary voltage on the bitline BLi by the charge sharing is V, the voltage of the bitline BLi before the sense amplification operation in the sense amplifier SA is VBL+V. Here, the bitline BLBi, theoretically, would maintain VBL of the precharge/equalization level, but substantially becomes about VBL+0.2(VBL+V) because of the mutual capacitance. As a result, such a decrease of the potential difference between the bitlines BLi and BLBi causes an amplifying operation in the sense amplifier SA to be under-performed.
To mitigate capacitive losses in sense amplification operations, a method of synchronously arranging bitlines in an open bitline architecture into a twisted architecture is disclosed in U.S. Pat. No. 5,383,159 and Japanese publication No. 61-255591. For example, in the U.S. Pat. No. 5,383,159, the bitlines of the bitline pairs that are synchronously activated are arranged in opposite directions of each other. While a bitline pair (e.g., BLi/BLBj of
FIG. 1
) is activated, the other bitline pair (e.g., BLj/BLBi) in the opposite direction is precharged/equalized to the bitline voltage (e.g.,VBL) by an equalization signal. Thereby, the mutual capacitance between bitlines can be suppressed. However, it becomes necessary to control the connecting states of precharge/equalization transistors and the timing of the equalization signal in order for the precharging and equalization operations of the bitlines to be controlled.
Because of the greater densities and speeds of state-of-the art DRAM, there is little time for an activation/inactivation of signals to control the sensing operations and timing between read and write signals. Thus, there is a need to address the capacitance problem.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a device capable of performing an effective data sensing operation in a high-integrated dynamic random access memory (DRAM).
It is another object of the invention to provide a constitution of a memory cell core circuit profitable for the high-integrated architecture, reducing mutual capacitance (or coupling capacitance) between bitline pair in DRAM.
It is still another object of the invention to provide a device capable of performing a reliable data sensing operation without employing an additional signal for precharging and equalizing bitlines in DRAM.
In order to attain the above objects, according to an aspect of the invention, there is provided a DRAM, situating each of bitlines of bitline pair that is synchronously activated in different blocks, and precharging the bitlines in response to an isolation signal which controls a connection between the bitline and the sense amplifier. Thus, it is not necessary to use an additional signal for precharging and equalizing the bitlines.
According to an aspect of the invention, there is provided a semiconductor memory device includes: a first and second blocks each disposed in sides of a sense amplifier, and formed of a plurality of bitlines; a circuit connecting a bitline coupled to memory cell of the first block and a complementary bitline of the second block to the sense amplifier, and charging a bitline coupled to memory cell of the second block and a complementary bitline of the first block up to a predetermined voltage in response to a signal.
According to another aspect of this invention, there is provided a semiconductor memory device including an isolation transistor connecting a bitline to a sense amplifier, and a precharge transistor connecting the bitline to reference voltage. In the device, a conductive line extends to a certain direction for transferring a signal for controlling the isolation and precharge transistors. A lower portion of the conductive line has a conductive active region of the isolation transistor and a conductive active region of the precharge transistor as a gate therein.
The invention will be better understood from the following detailed description of the exemplary embodiment thereof taken in conjunction with the accompanying drawings, and its scope will be pointed out in the appended claims.


REFERENCES:
patent: 5243574 (1993-09-01), Ikeda
patent: 5689461 (1997-11-01), Kaneko et al.
patent: 6097652 (2000-08-01), Roh
patent: 6285612 (2001-09-01), DeBrosse

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