Data sense arrangement for random access memory

Details Data sense arrangement for random access memory Data sense arrangement for random access memory

1997-11-06

2000-12-05

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Differential sensing

365208, 36518905, G11C 702

Patent

active

061575879

ABSTRACT:
A sensing circuit (30) for a random access memory (10) is disclosed. A CMOS sense amplifier (32) is coupled between bit line pairs which connected to I/O lines by a passgate (N4/N5). A pair of cross-coupled transistors (N6/N7) activated in synchronism with the passgate (N4/N5) is also disposed between the bit lines. The I/O line pairs each include a pair of cross coupled p-channel transistors (P4/P5). The combined action of the cross-coupled pairs (N6/N7) and (P4/P5) increase the sensing speed of the sensing circuit (30).

REFERENCES:
patent: 4608670 (1986-08-01), Duvvury et al.
patent: 4627033 (1986-12-01), Hyslop et al.
patent: 5127739 (1992-07-01), Duvvury et al.
patent: 5367486 (1994-11-01), Mori
patent: 5416371 (1995-05-01), Katayama
patent: 5777938 (1998-07-01), Nakamura

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