Data receiving method and circuit of digital communication syste

Details Data receiving method and circuit of digital communication syste Data receiving method and circuit of digital communication syste

1995-03-31

1998-01-27

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375371, 375373, 375376, 327149, 327158, 327161, H03D 324, H04L 700

Patent

active

057128847

ABSTRACT:
A data receiving circuit of a digital communication system which receives a transmitted input data bit column and input clock, comprising a first clock generator having a first delay that receives the input clock and outputs a first clock, a delay locked loop having secondary delay cells connected in series to each other which allow the first clock to be sequentially phase-delayed by 2.pi./2n and as a result, output secondary clocks, and which locks a phase difference between the first clock and an output of delay cell of 2.pi. radian, a phase detector for outputting a phase control signal which controls the delay time of the first delay cell so that the clocks outputted from the first clock generator and the delay locked loop can have rising edges in the middle point of a corresponding input data bit by detecting the phase difference between phases of the input data bit column and the clocks and then controlling the first delay cell, and a data register controlled by the clocks to receive the input data bit column.

REFERENCES:
patent: 5161173 (1992-11-01), Nordby
patent: 5488641 (1996-01-01), Ozkan
500 Mbyte/sec Data-Rate 512 Kbitsx 9 DRAM Using a Novel I/O Interface, N.Kushiyama et al. 1992 Symposium on VLSI Circuits digest of Technical Papers, pp. 66 -67.
Design of PLL-Based Clock Generation Circuits, Deog-Kyoon Jeong et al, IEEE Journal of solid-state circuits, vol. 22, No. 2, Apr. 1987, pp. 255 -261.

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