Data receiver

Details Data receiver Data receiver

2000-11-20

2002-04-02

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Input noise margin enhancement

C326S098000, C365S203000, C327S215000

Reexamination Certificate

active

06366113

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly, to a device and method for stabilizing a reference voltage in a data receiver.
2. Description of Prior Art
An early description of data receiver circuits can be found in “A 2.6-GByte/s multipurpose Chip-to-Chip interface”, by B. Lau et al., JSSC (November, 1998).
FIG. 1
shows a conventional data receiver
10
including first, second and third stages,
11
,
12
, and
13
, respectively. The first stage
11
includes a comparator for comparing input data (DIN) with a reference voltage (VREF), the second stage
12
includes a sense amplifier flip-flop (SAFF) for sensing and amplifying the output of the first stage
11
. The third stage
13
includes a latch such as an S-R latch, for latching the output of the second stage
12
.
The comparator of the first stage
11
is enabled by a bias voltage BIAS to compare the input data (DIN) with the reference voltage (VREF). Thus, the reference voltage (VREF) needs to be stable, without fluctuation. The reference voltage (VREF) and the bias voltage BIAS have predetermined DC levels, and are provided by a typical voltage generator. The SAFF of the second stage
12
is enabled in response to a clock signal (CLK), to amplify the result of the comparison by the first stage
11
. The third stage
13
stably latches the output of the second stage
12
using an S-R latch.
The reference voltage (VREF) needs to be stable, without fluctuation, within a level for the stable operation of the first stage
11
. Accordingly, a voltage generator generates the reference voltage to have a constant voltage level. However, the reference voltage (VREF) fluctuates while being applied to the first stage. That is, when the comparator of the first stage is operated while a bias voltage BIAS is being applied, the level of the reference voltage (VREF) is caused to fluctuate by coupling capacitance on the VREF line, including a coupling capacitor between a reference voltage (VREF) line and the drain X of an NMOS transistor MN, and a coupling capacitor between the VREF line and the source Y of the NMOS transistor MN. The coupling capacitor, which is inevitably and parasitically generated during the manufacture of a transistor, denotes a capacitor between a gate and a drain or between a gate and a source.
The fluctuation of the level of the reference voltage (VREF) caused by the coupling capacitor is referred to as kick-back noise. Kick-back noise can be reduced by connecting a shunt capacitor between the reference voltage (VREF) line and a ground voltage VSS (not shown). The shunt capacitor is set to have a greater capacitance than the coupling capacitor, and reduces the kick-back noise which is generated on the VREF line by the coupling capacitor.
However, when the shunt capacitor is increased, a problem is generated in that the voltage bounce of the ground voltage VSS is strongly coupled to the reference voltage (VREF).
The fluctuation in the voltage level of the VREF line can degrade the operating speed or cause a malfunction when comparing VREF with the voltage of input data DIN.
Therefore, a need exists for a data receiver which operates stably by preventing the reference voltage (VREF) from fluctuating due to the bounce of a ground voltage, kick-back noise or the like.
SUMMARY OF THE INVENTION
One embodiment of the present invention provides a data receiver for receiving input data in response to a clock signal. The data receiver includes a receiver for comparing the input data to a reference voltage in response to the clock signal, amplifying the result of the comparison, storing the logic level of the input data, and a counter coupling circuit for moderating the variation of the reference voltage caused by the receiver in response to an inverted clock signal.
Preferably, the receiver includes a first and a second precharging unit for initializing the receiver to a power supply voltage in response to the inversion of the clock signal, and a comparator for comparing the input data to the reference voltage in response to the clock signal.
The comparator preferably includes a first and a second inverter, cross-coupled, connected to the precharging units, respectively, wherein the output of the first inverter is connected to the input of the second inverter while the input of the first inverter is connected to the output of the second inverter, a first and a second comparing transistor connected to the outputs of the inverters, respectively, and controlled by the input data and the reference voltage, respectively, and a switching transistor connected between the comparing transistors and a ground voltage, and controlled in response to the clock signal.
The counter coupling circuit, according to a preferred embodiment of the present invention, includes a first transistor having a source to which a power supply voltage is connected, the first transistor controlled in response to the inverted clock signal which is connected to the gate of the first transistor, a second transistor having a source connected to the drain of the first transistor, the second transistor controlled in response to the reference voltage which is connected to the gate of the second transistor, a third transistor of a diode type having a source which is connected to the drain of the second transistor, and a gate and a drain which are connected to each other, and a fourth transistor having a drain connected to the drain of the third transistor, and a source to which a power supply voltage is connected, the fourth transistor controlled by the inverted clock signal which is connected to the gate of the fourth transistor.
According to another embodiment of the present invention, a data receiver is provided for receiving input data in response to a clock signal. The data receiver includes a first and a second precharging unit for initializing the data receiver to the power supply voltage in response to an inverted clock signal. The data receiver further includes a first and a second inverter, cross-coupled, connected to the first and second precharging units respectively, wherein the output of the first inverter is connected to the input of the second inverter while the input of the first inverter is connected to the output of the second inverter. The data receiver also includes a first and a second comparing transistor connected to the outputs of the first and the second inverter respectively, and controlled by the input data and the reference voltage, respectively. Preferably, the data receiver includes a switching transistor which is connected between the comparing transistors and a ground voltage, and controlled in response to the clock signal. The data receiver also includes a first transistor having a source to which a power supply voltage is connected, the first transistor controlled in response to the inverted clock signal which is connected to the gate of the first transistor, a second transistor having a source connected to the drain of the first transistor, the second transistor controlled in response to the reference voltage which is connected to the gate of the second transistor, a third transistor of a diode type having a source which is connected to the drain of the second transistor, and a gate and a drain which are connected to each other, and a fourth transistor having a drain connected to the drain of the third transistor, and a source to which a power supply voltage is connected, the fourth transistor controlled by the inverted clock signal which is connected to the gate of the fourth transistor.
According to still another embodiment of the present invention a data receiver includes a differential amplification flip flop for comparing an input data to a reference voltage, a latch having a set terminal and a reset terminal for latching an output of the differential amplification flip flop, a counter coupling circuit, connected to the reference voltage, for moderating fluctuations in the width of the reference voltage by about 30%.
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