Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1995-06-05
1997-07-08
Nguyen, Viet Q.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
36518901, 365196, 365207, 365205, 365190, G11C 1134
Patent
active
056468920
ABSTRACT:
In a data reading circuit, an output signal from a sense amplifier which outputs a signal having a level corresponding to a potential difference between an input/output line pair is output through a first tri-state inverter and a second tri-state inverter. An NMOS transistor for precharging is provided between an output node of the first tri-state inverter and an output node (N3) of the sense amplifier. When the sense amplifier and the first tri-state inverter are inactivated, this transistor is also inactivated. As a result, an output node of the second tri-state inverter and an output node of the sense amplifier are connected with this transistor therebetween, so that the output node of the sense amplifier is precharged to an intermediate potential. According to the structure as described above, in the data reading circuit, a fast access is implemented, operation of the circuit is stabilized, and the lack of balance between the access times is suppressed.
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Yasoji Suzuki, "Applied Technology for CMOS", Sanpo-Shuppan Co. Ltd., pp. 111, 114-115, Nov., 1976.
Masahiko Yoshimoto et al., "A Divided World-Line Structure in the Static RAM and Its Application to a 64K Full CMOS RAM", IEEE Journal of Solid-State Circuits, vol. SC-18, No. 5, pp. 479-485, Oct., 1983.
Masuda Shin'ichi
Segawa Hiroshi
Mitsubishi Denki & Kabushiki Kaisha
Mitsubishi Electric Engineering Co. Ltd.
Nguyen Viet Q.
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