Data read circuit used in semiconductor storage device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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36518909, 36518911, 365203, G11C 700

Patent

active

056711816

ABSTRACT:
When a data is read out from a memory cell, a current mirror circuit is operated in response to detection of potential variation of a first data line, so that charge of a second data line is discharged by the current mirror circuit. At this point, a control transistor interposed between the first data line and the second data line is operated in a saturation region. As a result, the impedance between the first data line and the second data line becomes substantially infinity, and the two data lines are substantially open-circuited. Thus, the current mirror circuit discharges merely the second data line with a small load capacitance in a short period of time, resulting in a high speed read operation. Therefore, even when the first data line, to which a large number of memory cells are connected, has a large load capacitance, the read rate is increased.

REFERENCES:
patent: 5115412 (1992-05-01), Tobita
patent: 5408438 (1995-04-01), Tanaka et al.

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