Data read circuit for use in semiconductor storage apparatus of

Details Data read circuit for use in semiconductor storage apparatus of Data read circuit for use in semiconductor storage apparatus of

1997-07-24

1998-12-01

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36523003, 36523006, 36523008, 365207, G11C 700, G11C 800

Patent

active

058448454

ABSTRACT:
There is disclosed a data read circuit for use in a semiconductor storage apparatus of a CMOS memory, in which a memory cell array of the semiconductor storage apparatus is divided into a plurality of memory blocks. Each of the memory blocks comprises a sense amplifier for amplifying a data output signal from a memory cell, and a read signal from the sense amplifier of the memory block selected by a block select signal obtained by decoding an external address is transmitted via a read data bus to a data output circuit having a data latch circuit. The data read circuit includes an NMOS or PMOS transistor for being turned on and off in response to a read signal from the sense amplifier in a data reading stage when the sense amplifier is activated. The NMOS transistor is disposed on each of the memory blocks, and has a drain connected to the read data bus and a grounded source. A first or second level signal is respectively outputted to the read data bus by turning on the NMOS or PMOS transistor when the read signal from the sense amplifier has a first level. On the other hand, the read signal from the sense amplifier is stopped from being outputted to the read data bus by turning off the NMOS transistor when the read signal from the sense amplifier has a second level.

REFERENCES:
patent: 5177573 (1993-01-01), Ukita et al.
patent: 5319595 (1994-06-01), Saruwatari
patent: 5481497 (1996-01-01), Yamauchi et al.

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