Data read circuit for semiconductor storage device

Details Data read circuit for semiconductor storage device Data read circuit for semiconductor storage device

1990-07-09

1991-11-26

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Precharge

36518905, 36518909, 365190, 365208, 3652335, 307530, G11C 700

Patent

active

050688316

ABSTRACT:
In a data read circuit, for a semiconductor storage device, data of a memory cell (11) selected according to an address is inputted to a sense amplifier (22) via a pair of complementary first data lines (N1 to N6). The sense amplifier outputs the inputted and amplified data to a pair of complementary second data lines (N7, N8). First switching means (Tr3) equalizes the pair of complementary first data lines (N5, N6) at the input side of the sense amplifier (22) by making the first data lines conductive with respect to each other. Second switching means (Tr4) equalizes the pair of complementary second data lines (N7, N8) by making the second data lines conductive with respect to each other. Third switching means (Tr5, Tr6) equalizes by making the pair of first data lines (N5, N6) at the input side of the sense amplifier (22) and corresponding ones of the pair of second data lines (N7, N8) conductive with respect to each other. Second equalizing pulse generator means (42) generates a second equalizing pulse (.PHI..sub.eq ') when the address is changed, and turns on the first switch means (Tr3) by applying the second equalizing pulse to a control terminal of the first switch means. First equalizing pulse generator means (41) generates a first equalizing pulse (.PHI..sub.eq) when the address is changed, and turns on the second and third switching means (Tr4, Tr5, Tr6) by applying the second equalizing pulse to gate terminals of the second and third switching means. The load capacitance ]C(.PHI..sub.eq ')] connected to an output terminal of the second equalizing pulse generating means (42) is set smaller than the load capacitance [C(.PHI..sub.eq)] connected to an output terminal of the first equalizing pulse generator means (41). The number of stages of logical circuits constituting the second equalizing pulse generator means (42) is smaller than the number of stages of logical circuits constituting the first equalizing pulse generator means (41). Accordingly, with this data read circuit for a semiconductor storage device, the second equalizing pulse (.PHI..sub.eq ') from the second equalizing pulse generator means (42) is established earlier than the first equalizing pulse (.PHI..sub.eq) from the first equalizing pulse generator means (41).

REFERENCES:
patent: 4943944 (1990-07-01), Sakui et al.

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