Data processor with multiple register queues

Details Data processor with multiple register queues Data processor with multiple register queues

1993-12-23

2000-04-11

Myers, Paul R.

Electrical computers and digital data processing systems: input/

Input/output data processing

G06F 1300

Patent

active

060498390

ABSTRACT:
A data processor includes a register group having registers of the number larger than the number of registers which can be designated by a register specifier field of an instruction. The register group consists of a plurality of register queues with respect to logical register numbers designated in the instruction, each register queue including a plurality of physical registers. In the data processor, a physical register number forming section is provided for converting the logical register number to a physical register number in the register queue corresponding to the logical register number, by using queue control information designated in the register specifier field and read/write information decided by the kind of the instruction and the position of the register specifier field in the instruction.

REFERENCES:
patent: 5134562 (1992-07-01), Hattori et al.
patent: 5148542 (1992-09-01), Sakuma et al.
Hironaka et al. of Kyushu University, "Benchmarking a Vector-Processor Prototype Based on Multithreaded Streaming/FIFO Vector (MSFV) Architecture", International Conference on Supercomputing, 1992.
J. H. Hennessy and D.A. Patterson, "Computer Architecture: A Quantitative Approach", Morgan Kaufmann Publishers, Inc., 1990 pp. 450-454.
Hideo Wada, Shun Kawabe, Toshihiko Odaka "Hitachi supercomputer S-820 overview", proceeding of Supercomputing Europe '89, pp. 139-147.
P.Tirumalai, M.Lee, and M.Schlansker: Parallelization of Loops with Exits on Pipelined Architectures, Proceedings of Supercomputing '90, pp. 200-212 (1990).
K. Murakami: Hyperscaler Processor Architecture-The Fifth Approach to Instruction-Level Parallel Processing,JSPP '91 Proceedings, pp. 133-140 (1991).
Wm.A.Wulf: Evaluation of the WM Architecture, Proceedings of the 19th Annual ISCA, pp. 382-390(1992).
J.C.Dehnert, P.Y. T.Hsu, and J.P.Bratt: Overlapped Loop Support in the Cydra 5, ASPLOS -III Proceedings, pp. 26-38 (1989(.
H.Nakamura, H.Imori, K.Nakazawa, T.Boku, I.Nakata, Y.Yamashita, H.Wada, and Y. Inagami: A Scalar Architecture for Pseudo Vector Processing based on Slide-Windowed Registers, Conference Proceedings of 1993 International Conference on Supercomputing, pp. 298-307(1993).

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