Data processor, semiconductor memory device and clock...

Details Data processor, semiconductor memory device and clock... Data processor, semiconductor memory device and clock...

2005-05-17

2005-05-17

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S241000

Reexamination Certificate

active

06894939

ABSTRACT:
In a data processor which comprises a semiconductor memory device, a potential on a bit line of the semiconductor memory device is monitored at the end of a precharge, required for the semiconductor memory device, to detect an anomalous frequency of a clock applied from the outside. The anomalous frequency is detected by determining whether or not the potential on the bit line has reached a predetermined potential. When the potential on the bit line has not reached a predetermined potential, the operation of a CPU is reset.

REFERENCES:
patent: 5386150 (1995-01-01), Yonemoto
patent: 6580653 (2003-06-01), Yamanaka
patent: 6717865 (2004-04-01), Laurent
patent: 2002-055130 (2002-02-01), None

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