Electrical computers and digital processing systems: memory – Address formation – Combining two or more values to create address
Patent
1993-11-19
2000-11-28
Lane, Jack A.
Electrical computers and digital processing systems: memory
Address formation
Combining two or more values to create address
711 2, G06F 1200
Patent
active
061548278
ABSTRACT:
A data processor capable of accessing data with the data processing capacity of a central processing unit (CPU), even if the data processing capacity of the CPU within the data processor is larger than the data output capacity of the memory storing the data. Such a data processor includes a temporary storage unit for storing the data outputted from the memory corresponding to the first and second address signals, respectively, applied sequentially on first and second storage areas in response to first and second storage control signals applied sequentially, and for generating the data stored in each area to the CPU at one time in response to a data output control signal of the CPU; a signal generating unit for generating the first and second storage control signals applied to the temporary storage unit in response to the least address signal of address signals provided from the CPU and a system clock, and for generating the address extension signal alternately having the first and second logic states during generating period of the data output control signal, in order to extend the address for the data; and an address signal supplying unit for jointing the address extension signal and the rest address signals excepting the least address signal of the CPU, during generating period of the data output control signal, and for supplying the jointed signal to the memory as the first and second address signals.
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Bushnell Esq. Robert E.
Lane Jack A.
Samsung Electronics Co,. Ltd.
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