Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
1997-09-12
2001-01-16
Follansbee, John A. (Department: 2783)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C712S032000, C712S037000, C712S039000, C712S229000, C712S231000
Reexamination Certificate
active
06175913
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data processing unit, such as a microprocessor or microcontroller, with debug capabilities. Whereas in the first microprocessor systems debugging of software could only be done by software which did not allow any real time analysis, nowadays microprocessors have special debug hardware on chip. This debug hardware allows to program breakpoints to control the flow of a program which has to be analyzed. Therefore, the breakpoints do not have to be simulated by software anymore, but still even hardware generated breakpoints may interrupt the program and control will be taken by the respective debug software. In many real time applications, program flow may not be interrupted. Thus, for many real time applications an in circuit emulator might still be necessary.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a data handling unit with additional debug hardware which provides an efficient debug support and minimizes the need of in circuit emulators. This object is achieved by a data processing unit, comprising a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus, a debug unit being coupled to said bus, a protection unit coupled with the bus and with the debug unit for protecting access on the bus. The protection unit is programmable to operate in a protecting mode in which the bus can be protected and in a debug mode in which a signal is sent to the debug unit, whereupon the debug unit generates a debug signal.
In a further embodiment, the data processing unit further comprises an interrupt controller coupled with an interrupt input of the central processing unit. The debug signal is fed to said interrupt controller and upon a debug event an interrupt is generated. The interrupt can be assigned any priority, thus allowing to service a short debug routine and to avoid interrupting critical real time routines with higher priorities.
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Arnold Roger D.
Chesters Eric
Fleck Rod G.
Follansbee John A.
Nguyen Dzung C.
Siemens AG
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