Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1998-03-10
2001-03-13
Wiley, David A. (Department: 2781)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
Reexamination Certificate
active
06202163
ABSTRACT:
BACKGROUND OF INVENTION
The present invention relates to a data processing circuit having a plurality of elements, wherein said elements operate in response to coded instructions while receiving clocking signals.
Data processing environments are known in which elements operate in response to decoded instructions while receiving clocking signals. A clocking signal is often generated by a quartz oscillator or similar and the signals are distributed throughout the circuit so as to provide a common reference for manipulations performed within the elements. The overall processing speed of a device may be increased by increasing the frequency of the clock although an upper bound will be reached beyond which satisfactory operation is not possible. Furthermore, the clocking of elements within a circuit also results in power dissipation which is an important factor when considering apparatus driven by a limited power supply, such as that provided by a battery.
A known approach towards reducing power consumption is to effectively stop the operation of the clock when processing within the circuit is not required. The chip is said to be placed in its idle mode and additional components are required in order to selectively place the circuit in one of its operational modes; that is in its active power dissipating mode or its reduced power dissipation idle mode. A problem with this approach is that the stopping of the clock results in a total shut down of the circuit therefore periods during which the clock may actually be stopped are limited and the power saving may be off-set by the additional measures that must be taken when selecting periods of shut down.
BRIEF SUMMARY OF INVENTION
According to a first aspect of the invention there is provided a data processing circuit comprising a plurality of elements, wherein said elements operate in response to decoded instructions while receiving clocking signals, comprising means for identifying instruction types; and means for enabling or disabling clocking signals to at least one of said elements in dependence upon whether said element is required for the execution of said instruction type.
According to a second aspect of the present invention, there is provided a data processing circuit comprising a plurality of elements, wherein said elements operate in response to decoded instructions while receiving clocking signals, comprising means for identifying instruction types, and means for enabling or disabling at least one of said elements in dependence upon whether said element is required for the execution of said instruction type.
In a preferred embodiment, the elements include a data processing unit and a data address generating unit and the data processing unit may include more than one multiplier and more than one arithmetic unit with co-operating multiplexed circuits.
Preferably, the means for identifying instruction types is an instruction decode unit having an instruction type decoder and the instruction type decoder may be configured to gate clock signals. Preferably, gated clock signals and input instructions are supplied to a plurality of instruction decoders. Optionally, an instruction type decoder is configured to enable or disable instruction decoders for respective instruction types, and the instruction decoders are configured to gate clock signals.
According to a third aspect of the present invention, there is provided a method of processing data, wherein a plurality of elements within a data processing circuit operate in response to decoded instructions while receiving clocking signals, comprising steps of identifying instruction type; and enabling or disabling clocking signals to at least one of said elements in dependence upon whether said element is required for the execution of said instruction type.
According to a fourth aspect of the present invention there is provided a method of processing data, wherein a plurality of elements within a data processing circuit operate in response to decoded instructions while receiving clocking signals, comprising steps of identifying instruction types, and enabling or disabling at least one of said elements in dependence upon whether said element is required for the execution of said instruction type.
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European Search Report.
Gabzdyl Rebecca
Lansdowne Richard
McGovern Brian Patrick
Nokia Mobile Phones Limited
Perman & Green LLP
Wiley David A.
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