Data processing apparatus and method for identifying...

Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...

Reexamination Certificate

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Reexamination Certificate

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07831815

ABSTRACT:
A data processing apparatus is provided comprising a processing unit for executing instructions, a cache structure for storing instructions retrieved from memory for access by the processing unit, and profiling logic for identifying a sequence of instructions that is functionally equivalent to an accelerator instruction. When such a sequence of instructions is identified, the equivalent accelerator instruction is stored in the cache structure as a replacement for the first instruction of the sequence, with the remaining instructions in the sequence of instructions being stored unchanged. The accelerator instruction includes an indication to cause the processing unit to skip the remainder of the sequence when executing the accelerator instruction.

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Hazelwood et al.; Managing Bounded Code Caches in Dynamic Binary Optimization Systems; 2006; ACM Transactions on Architecture and Code Optimization.
Stitt et al.; Dynamic Hardware/Software Partitioning: A first Approach; 2003; DAC '03.
Lysecky et al.; Warp Processors; 2006; ACM Transactions on Design Automation of Electronic Signals.

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