Data path for high speed high bandwidth DRAM

Details Data path for high speed high bandwidth DRAM Data path for high speed high bandwidth DRAM

1998-07-02

1999-08-03

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

G11C 1300

Patent

active

059333723

ABSTRACT:
A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array bit lines and data input/output connections are distributed around the memory to increase speed. Multiplexed latch circuitry is provided which incorporates separate data paths for both data read and write operations.

REFERENCES:
patent: 4303986 (1981-12-01), Lans
patent: 5666312 (1997-09-01), Robertson

Affiliated with

Also associated with

Rating

Data path for high speed high bandwidth DRAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data path for high speed high bandwidth DRAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data path for high speed high bandwidth DRAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-855675