Data path for high speed high bandwidth DRAM

Details Data path for high speed high bandwidth DRAM Data path for high speed high bandwidth DRAM

1997-02-26

1998-09-01

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518902, 36523002, G11C 1300

Patent

active

058019960

ABSTRACT:
A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array bit lines and data input/output connections are distributed around the memory to increase speed. Multiplexed latch circuitry is provided which incorporates separate data paths for both data read and write operations.

REFERENCES:
patent: 5666312 (1997-09-01), Robertson

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