Data packet processing device

Electrical computers and digital data processing systems: input/ – Input/output data processing – Concurrent input/output processing and data transfer

Reexamination Certificate

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Details

C710S029000, C710S031000, C710S033000, C710S052000, C710S053000, C710S056000

Reexamination Certificate

active

07925798

ABSTRACT:
A device for data packet processing is disclosed. In one embodiment, the device includes a processor implemented on a chip, an on-chip internal segment memory accessible by the processor, an off-chip external segment memory and a data transfer channel between the internal segment memory and the external segment memory. The external segment memory comprises first and second memory segments wherein the first and second memory segments are different in size.

REFERENCES:
patent: 7418568 (2008-08-01), Maly
patent: 2004/0141650 (2004-07-01), Hansson et al.
patent: 2005/0021874 (2005-01-01), Georgiou et al.
patent: 2005/0025140 (2005-02-01), Deforche et al.
patent: 2006/0149915 (2006-07-01), Maly
patent: 2007/0030899 (2007-02-01), Iguchi et al.
patent: 2007/0060142 (2007-03-01), Reznik et al.
patent: 2009/0043972 (2009-02-01), Kamiko et al.
patent: 2006080897 (2006-08-01), None

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