Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2005-02-15
2009-06-09
Hafiz, Tariq R. (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S029000, C710S057000, C710S100000, C710S305000, C370S252000, C370S412000
Reexamination Certificate
active
07546400
ABSTRACT:
Data packet buffering system comprising a data buffer for buffering data packets, a first counter (24) preloaded with the data packet size (32) and decremented at each read clock signal of a number of logical units corresponding to the width of the output bus (18), a second counter (28) preloaded with the data packet size and decremented at each write clock signal of a number of logical units corresponding to the width of the input bus (14), the decrementation of the second counter being started at the same time as the decrementation of the first counter by a start counter signal (38), and a threshold unit (52) for determining the minimum threshold from the contents of the second counter when the first counter has reached zero and providing the minimum threshold to a buffer management logic unit a buffer management logic unit (22) providing write grant signals when data may be read from the data buffer and sent to an output device.
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Gorzegno Fabrice
Guenoun Lionel
Roman Denis
Suzzoni Jean-Pierre
Blecker Ira D.
Hafiz Tariq R.
International Business Machines - Corporation
Li Wenjie
Yu Henry
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