Data output driver of semiconductor memory device

Details Data output driver of semiconductor memory device Data output driver of semiconductor memory device

2003-02-27

2004-05-11

Auduong, Gene (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189070, C365S221000

Reexamination Certificate

active

06735128

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a data output driver, and more particularly to a data output driver which reduces a skew in an interface circuit of a semiconductor memory device.
2. Description of the Prior Art
As generally known in the art, data sequentially written to a register in a semiconductor memory device are sequentially read and outputted from the register in a first-in-first-out (FIFO) manner. At this time, supposing an increased amount of a current flowing through a ground in a data output driver is I
1
when one of all input signals is inverted from a low level to a high level, the increased amount thereof becomes N×I
1
when all the input signals are inverted from a low level to a high level (N indicates a width of a bus). Since such a great change in current changes the ground voltage, thus reducing the voltage between a gate and a source of a MOS transistor forming the data output driver, driving performance of the data output driver deteriorates. That is, the degree of signal delay varies according to the pattern of data.
When one input signal among all the input signals is inverted from a low logic level to a high logic level, a minimal delay TDmin occurs. When all the input signals are inverted from a low logic level to a high logic level, a maximal delay TDmax occurs. Skew is defined by the following equation 1.
Equation 1
SKEW=|TDmax−TDmin|
As shown in equation 1, when the difference between the maximal delay TDmax and the minimal delay TDmin is great, the skew becomes greater to reduce the timing margin in a semiconductor memory device. The following table 1 indicates results which models a channel of a Rambus DRAM and measures when the internal data of a chip reaches a memory controller in a READ mode.
TABLE 1
(unit: nsec)
tdly0
tdly1
tdly2
tdly3
tdly4
tdly5
tdly6
tdly7
10000000
3.268
0
0
0
0
0
0
11000000
3.300
3.299
0
0
0
0
0
0
11100000
3.344
3.344
3.342
0
0
0
0
0
11110000
3.367
3.368
3.367
3.362
0
0
0
0
11111000
3.394
3.396
3.397
3.392
3.375
0
0
0
11111100
3.414
3.417
3.418
3.414
3.405
3.404
0
0
11111110
3.435
3.439
3.441
3.438
3.432
3.434
3.434
0
11111111
3.456
3.460
3.463
3.461
3.460
3.464
3.467
3.465
In the table 1, tdly
2
indicates the time required that a signal inputted from a third pin DQ
2
is outputted and reaches the memory controller. A tdly
2
of “0” indicates that a signal transmission does not occur because no transitions of a signal occur in an observing moment. As shown in table 1, when the number of transitions to a logic high level is one, the delay time in an input signal is 3.268 nsec. In contrast, when the number of transitions to a logic high level is eight, the delay time in an input signal is 3.456 nsec. The difference between the delay times according to patterns, that is the skew, is 188 psec.
SUMMARY OF THE INVENTION
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a data output driver which improves the timing margin of a memory operation by reducing a skew related to a data output in a semiconductor memory device.
In order to accomplish the object, there is provided a data output driver of a semiconductor memory device comprising: a register for receiving and storing a plurality of first parallel data in synchronization with a clock signal and for outputting a plurality of second parallel data; a controller for comparing a plurality of parallel data being inputted to the register with a plurality of parallel data having previously been inputted to the register in response to a delayed clock signal obtained by delaying the clock signal for a predetermined time and calculating the number of data transitions based on the comparison result, and for generating a control signal according to the calculated number of data transitions; a clock signal delay part for delaying the clock signal according to a logic level of the control signal from the controller in order to generate a pair of corrected clock signals; a data selecting part for selectively outputting odd- or even-numbered data among the plurality of second parallel data; and an output driving part for buffering and outputting output data of the data selecting part.


REFERENCES:
patent: 5594373 (1997-01-01), McClure
patent: 5596297 (1997-01-01), McClure et al.
patent: 5767715 (1998-06-01), Marquis et al.
patent: 5805603 (1998-09-01), Araki et al.
patent: 5917760 (1999-06-01), Millar
patent: 5991232 (1999-11-01), Matsumura et al.
patent: 6072743 (2000-06-01), Amano et al.
patent: 6151274 (2000-11-01), Takemae et al.

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