Data output device and method of semiconductor device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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C365S189060, C365S189070

Reexamination Certificate

active

07423914

ABSTRACT:
The data output device comprises a first comparator for comparing first output data with arbitrary output data on a bit-by-bit basis and outputting a first pre-flag signal, a second comparator for comparing second output data with the first output data on a bit-by-bit basis and outputting a second pre-flag signal, a first logic unit for performing a logic operation with respect to pre-flag signal and an arbitrary data inversion flag signal and outputting a first data inversion flag signal, a second logic unit for performing a logic operation with respect to the second pre-flag signal and the first data inversion flag signal and outputting a second data inversion flag signal, a first repeater for inverting or non-inverting and outputting a plurality of bits contained in the first out put data, and a second repeater for inverting or non-inverting and outputting a plurality of bits contained in the second output data.

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patent: 2005/0002223 (2005-01-01), Coteus et al.
patent: 6289154 (1994-10-01), None
Kwack et al., “A Pre-DBI(PDBI) method for Giga Hz DRAM's”, The 12th Korean Conference on Semiconductors, COEX Conference Center, http://kcs.cosar.or.kr, Feb. 24-25, 2005, pp. 12, 395-396.

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