Data output control circuit for semiconductor memory device

Details Data output control circuit for semiconductor memory device Data output control circuit for semiconductor memory device

1997-07-25

1999-04-20

Nelms, David

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

3652335, 365191, G11C 1604

Patent

active

058963235

ABSTRACT:
A data output control circuit for a semiconductor memory device sequentially transmits input data via a main amplifier controlled by an address transition detecting signal, a multiplex/latch unit, a data output buffer and an output operator. The data output control circuit prevents false data output, which also improves data processing speed by using a control signal. The data output control circuit includes an output control unit that converts an address transition detecting signal into a kill signal. The kill signal is applied to the data output buffer to cause the output operator to generate a zero level signal based on the address transition detecting signal. The data output control circuit enables the output operator to generate a zero level signal by applying the kill signal to the data output buffer when the transition of an address signal is detected. Accordingly, an interval for a data reversal or a full swing is prevented to enhance data processing speed and reduce current consumption.

REFERENCES:
patent: 5648932 (1997-07-01), Kang
patent: 5694361 (1997-12-01), Uchida
patent: 5715212 (1998-02-01), Tanida et al.

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