Data output control circuit

Details Data output control circuit Data output control circuit

2005-12-20

2005-12-20

Smith, Zandra V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S193000, C365S194000, C365S233100

Reexamination Certificate

active

06977848

ABSTRACT:
A data output control circuit for use in a synchronous semiconductor memory device, which has a plurality of CAS latency modes, includes a signal generating unit for generating an internal signal corresponding to an input command; a CAS latency mode control unit for outputting the internal signal as a controlled internal signal; a signal shifting unit for generating a plurality of shifted signals by synchronizing the controlled internal signal with a DLL clock signal; and a data output enable signal generating unit for outputting one of the plurality of shifted signals as a data output enable signal depending on a plurality of control signals, wherein each of the plurality of control signals corresponds to two or more continuous CAS latency modes.

REFERENCES:
patent: 6205062 (2001-03-01), Kim et al.
patent: 6215726 (2001-04-01), Kubo

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