Data output circuit, intermediate potential setting circuit, and

Details Data output circuit, intermediate potential setting circuit, and Data output circuit, intermediate potential setting circuit, and

1997-06-25

1998-11-03

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

36518909, G11C 700

Patent

active

058319085

ABSTRACT:
A data output circuit includes a ground terminal, a power supply terminal, an output terminal having parasitic capacitor, a PMOS transistor having a current path connected between the power supply terminal and the output terminal and a gate to which one of first and second complementary data signals is supplied, an NMOS transistor having a current path connected between the ground terminal and the output terminal and a gate to which the other of the first and second complementary data signals is supplied, and a gate control section for feeding back the potential of the output terminal to the gates of the transistors and to change the potential of the output terminal toward a predetermined intermediate level within the voltage ranged between the ground terminal and the power supply terminal before the first and second complementary data signals are supplied. An intermediate potential setting circuit includes two MOS transistors having different conductivity types and connected in series between reference power supplies, first and second gate control units, respectively connected to gates of the transistors, for separately ON/OFF-controlling the transistors, a load capacitor connected between the connection node of the transistors and one of the reference power supplies,.a control unit, connected between the connection node and the first and second gate control units, for feeding back a potential of the connection node to the first and second gate control units to selectively perform control to turn on the transistors, an external control unit for externally supplying a control signal to the first and second gate control units, and an output terminal, connected to the connection node, for extracting an intermediate potential output as a potential of the load capacitor.

REFERENCES:
patent: 4272832 (1981-06-01), Ito
patent: 4300213 (1981-11-01), Tanimura et al.
patent: 4988888 (1991-01-01), Hirose et al.
patent: 5166558 (1992-11-01), Ohsawa
patent: 5179300 (1993-01-01), Roland et al.
patent: 5306965 (1994-04-01), Asprey
patent: 5377149 (1994-12-01), Gaultier
patent: 5420525 (1995-05-01), Maloberti et al.
patent: 5450019 (1995-09-01), McClure et al.
patent: 5491432 (1996-02-01), Wong et al.

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